Co-Packaged Optics Market Report 2026-2036: Product Benchmarking of Spectrum-X, Quantum-X, and Bailly Platforms, Start-Up Innovation Mapping, and Foundry Comparisons - ResearchAndMarkets.com - Business Wire

Skyler: Welcome to Line Rate — the show tracking the chips, standards, and companies building the fabric that powers A I infrastructure. I'm Skyler Monroe, and if it moves bits between accelerators, racks, or datacenters, we cover it here. Big thanks to our sponsors: Ada, who helps organizations actually integrate A I into their real workflows, and Zen Semiconductor, an umbrella company with a portfolio of businesses across the silicon industry, including Ada for A I deployment. Today we've got a packed show — co-packaged optics is having a moment, copper is fighting back harder than you might expect, Meta is laying out an open networking vision at OCP, and Dell is putting numbers behind the A I datacenter buildout. Let's get into it. Skyler: First up, ResearchAndMarkets dropped a market report on co-packaged optics running from 2026 all the way to 2036, and it's one of the more substantive looks at the CPO competitive landscape I've seen in a while. The headline framing is a product benchmarking exercise across three named platforms — Spectrum-X, Quantum-X, and something called the Bailly platform — plus a startup innovation map and foundry comparisons. Let's unpack what that actually means for people building or buying into this space. Skyler: Spectrum-X is NVIDIA's AI networking platform — it's the combination of the Spectrum-4 Ethernet switch ASIC and the BlueField-3 DPU, and it's been NVIDIA's answer to the question of how you build a high-performance Ethernet fabric for A I training without going InfiniBand. Quantum-X is the InfiniBand side of that house — NVIDIA's current-generation InfiniBand switch and NIC family targeting the tightest-coupled, lowest-latency A I cluster use cases. The Bailly platform is less commonly discussed in the trade press, so it's notable that it shows up in a 2026-2036 forecast — Bailly is associated with Intel's co-packaged optics development work, and it signals that Intel's CPO roadmap is being taken seriously as a distinct competitive vector in this market. Skyler: The core technical problem that CPO is solving is this: as switch ASICs have scaled — we're talking 51.2 terabits per second today, with 102.4 on the roadmap — the pluggable optical module ecosystem that's served us for decades starts to hit a wall. The power density and signal integrity requirements of driving hundreds of SerDes lanes at 200 gigabaud and beyond make the traditional pluggable form factor increasingly painful. Co-packaging the optical engine directly with the switch die, or on the same substrate in a multi-chiplet package, cuts the reach of those electrical traces dramatically and reduces power significantly. Skyler: What the foundry comparison section of this report is really getting at is that CPO is not just a photonics problem — it's a packaging and process integration problem. You need a silicon photonics process that can sit on or near a leading-edge CMOS die, and you need advanced packaging — think silicon interposers, embedded bridge dies, or fan-out panel-level packaging — to bring it all together. TSMC, Intel Foundry, GlobalFoundries, and Tower Semiconductor all have different positions on the silicon photonics side, and the report apparently maps how those foundry capabilities translate into product differentiation. That's exactly the right question to be asking over a ten-year horizon, because whoever locks up the process integration recipe earliest has a significant moat. Skyler: The startup innovation mapping piece is also genuinely interesting. There's a real cohort of companies — Ayar Labs, Celestial A I, Lightmatter, Ranovus, and others — working on everything from in-package photonic interconnects to optical computing fabrics. The 2026-2036 window is meaningful because most analysts expect CPO to start appearing in production switch hardware at scale around 2026-2027, so we're essentially at the threshold year for this technology. If you're an investor or an architect making platform decisions, understanding where the startup ecosystem is innovating relative to the merchant silicon incumbents is exactly the kind of map you need. Skyler: Story two takes us to the OCP Summit 2025, where Meta's engineering team published a detailed blog laying out their vision for open networking hardware for A I. If you're not tracking OCP — the Open Compute Project — it's the consortium that Meta, Microsoft, and others have used to push open, disaggregated hardware designs into the datacenter supply chain. And Meta's 2025 summit post is a clear signal about where they think the networking layer needs to go to keep pace with A I workload scaling. Skyler: The core argument Meta is making is that A I training and inference at their scale requires a fundamentally different networking architecture than traditional cloud workloads. The traffic patterns are different — you've got massive all-reduce collectives in training, dense east-west flows that are highly synchronized, and latency tails that matter enormously because a single slow link can stall hundreds of accelerators. Pluggable merchant silicon with commodity NOS software wasn't designed with that in mind. Skyler: What Meta is pushing for at OCP is disaggregation and openness across multiple layers simultaneously. On the silicon layer, they want switch ASICs with richer telemetry and programmability surfaces — not just forwarding, but congestion control hooks, in-network compute primitives for collective operations, and better support for the kinds of adaptive routing that A I fabrics need. On the optics layer, they're pushing hard on co-packaged optics as the path to the power budgets they need at 51.2T and beyond. And on the software layer, they want open APIs and control planes that let them build fabric management that's tightly integrated with their A I training orchestration. Skyler: The competitive implication here is significant. When a hyperscaler with Meta's purchasing volume shows up at OCP and says "this is what we need," the merchant silicon vendors listen. Broadcom, Marvell, and others have all been responsive to hyperscaler requirements in previous OCP cycles — the Tomahawk and Tofino roadmaps both carry fingerprints of hyperscaler input. So when Meta says they need better collective offload and richer telemetry, expect to see that reflected in next-generation ASIC roadmaps. Skyler: There's also a subtler strategic point here about Meta's relationship with NVIDIA. Meta is one of the largest buyers of NVIDIA GPUs on the planet, but they are also deeply invested in not being completely dependent on NVIDIA's networking stack. The Spectrum-X and Quantum-X InfiniBand ecosystems are tightly integrated with NVIDIA's software layer, and Meta has historically preferred to control their own networking. So the OCP open networking push is partly a hedge — building a supply chain and a standards ecosystem that gives them architectural freedom regardless of which accelerator they're buying in any given generation. Skyler: Meta also highlighted their work on disaggregated chassis and modular line-card designs within OCP, which is relevant because it affects how quickly operators can refresh the optical layer independently of the switching silicon. That's a non-trivial operational consideration when CPO starts shipping — you don't want to be locked into a chassis that forces a full switch replacement every time the optics generation turns over. Skyler: Story three comes from The Next Platform, and it's a Dell data point that I think is worth taking seriously even if it sounds like a vendor talking-point headline. Dell is projecting that A I workloads will drive 75 percent of datacenter demand by 2030. Let's sit with that number for a second. Skyler: 75 percent is a striking figure, and the natural instinct is to be skeptical — Dell has obvious commercial reasons to hype A I infrastructure spend. But when you look at the underlying drivers, the directional logic is pretty solid. GPU and accelerator clusters are fundamentally more power-dense and bandwidth-hungry per rack unit than general-purpose compute. An H100 or Blackwell server draws ten times the power of a typical CPU server and requires dramatically more networking bandwidth to stay fed. So even if A I represents a smaller fraction of total server unit shipments, it can dominate power consumption, cooling capacity, and networking infrastructure spend. Skyler: The 2030 timeframe is also interesting because it aligns with multiple technology transitions that are already in motion. The shift from air cooling to direct liquid cooling is accelerating because you simply cannot remove 60-100 kilowatts per rack with air at reasonable scale. Co-packaged optics starts appearing in production hardware. The next two or three generations of accelerators ship, each with higher TDP and higher memory bandwidth requirements. And the software stack for distributed training and inference continues to mature, enabling larger and more interconnect-intensive model architectures. Skyler: From a fabric and interconnect standpoint, what the Dell projection really means is that the design center for datacenter networking is shifting. The question is no longer "how do I build a network that handles a mix of east-west and north-south traffic with occasional bursts" — it's "how do I build a network that is optimized for highly synchronized, all-to-all collective communication at petabit-per-second aggregate bandwidth." That's a different answer in terms of topology, congestion control, and the latency profile you're targeting. Skyler: It also has implications for the merchant silicon roadmap cadence. If A I fabric is 75 percent of the demand by 2030, then the ASIC vendors who are investing in collective offload, in-network reduction, and ultra-low latency forwarding are betting correctly. And the optical module vendors who are investing in CPO and 200G-per-lane coherent technology are positioning for the right demand curve. The Dell number, taken with appropriate skepticism about precision, points in the right direction. Skyler: One more thing worth noting — Dell's server and storage business is deeply intertwined with their PowerScale and PowerEdge lines for A I, but their networking exposure is real and often underappreciated. Dell has OEM relationships across the networking stack and is one of the larger resellers of merchant switch hardware into enterprise and mid-market customers who are now trying to build A I infrastructure. So when Dell talks about A I driving datacenter demand, they're also implicitly talking about their own go-to-market evolution. Skyler: Story four is one I find genuinely fascinating — a Semivision piece titled "The Last Line of Defense for Copper: The Rise of Co-Packaged Copper in A I Data Center Interconnect Architectures." The framing of copper as a last line of defense is a little dramatic, but the technical argument is real and I think it's underappreciated in a lot of the optics-centric coverage you see. Skyler: Co-packaged copper, or CPC, is the idea that you don't have to go directly from traditional pluggable copper cables to co-packaged optics — there's a meaningful intermediate step where you co-package a copper electrical interface directly with the switch or compute die. The logic is that at short enough distances — we're talking about within a rack or between adjacent racks — a well-designed co-packaged copper interface can deliver comparable signal integrity and power efficiency to optics, without the cost and complexity of silicon photonics integration. Skyler: The signal integrity fundamentals here are worth understanding. As SerDes rates have scaled — 56 gigabaud, 112 gigabaud, and now 200 gigabaud on the roadmap — the reach of copper at those data rates over passive copper cable has gotten shorter. At 112 gigabaud PAM4, you're looking at maybe one to three meters of passive copper reach before you need active equalization or retiming. At 200 gigabaud, that shrinks further. But within a rack, one to three meters covers most of your connectivity needs. Skyler: What CPC does is move the equalization and retiming circuitry off the line card and into a co-packaged module that sits at the cable termination point — either at the switch end, the server end, or both. That lets you run the actual cable passively and cheaply, while the intelligence lives in a compact package that can be optimized for power and signal quality. The advantage over CPO is primarily cost and manufacturing maturity — silicon photonics packaging is still expensive and the yields are improving but not yet at the level of mature copper IC packaging. Skyler: The competitive tension between CPC and CPO is really a question of which distance ranges end up being dominant in A I fabric architectures. If hyperscalers move to rack-scale or pod-scale architectures where most of the inter-GPU connectivity is within a few meters, CPC has a real role to play. If the trend goes toward larger clusters where you need to reach across longer distances within a building — 10, 20, 50 meters — then optics is the only viable answer and CPO is the right form factor. The honest answer is that real A I datacenters will have both, and the fabric architecture will be heterogeneous. Skyler: There are also power consumption arguments for CPC that are worth taking seriously. In a dense GPU cluster, every watt you spend on interconnect is a watt you're not spending on compute. Copper at short reach can be more power efficient than optics in some configurations because you avoid the laser driver and photodetector power overhead. The Semivision piece is arguing that this efficiency window is large enough and lasts long enough — even through the 200 gigabaud generation — that CPC deserves a serious architectural role, not just a transitional placeholder role while CPO matures. Skyler: Companies like Marvell, Credo Semiconductor, and Astera Labs have been investing in the active copper and retimer space that feeds into CPC architectures. It's not a glamorous part of the market to talk about — "we make retimers" doesn't get the press that "we make co-packaged silicon photonics" does — but the TAM is real and the design wins in major hyperscaler builds validate that copper isn't going away as fast as the optics-centric narrative sometimes suggests. Skyler: Story five brings us back to CPO — this time from Electronics360, with a piece specifically about bringing co-packaged optics to rack-scale A I infrastructure. This is where the rubber meets the road on the technology we've been discussing, and the rack-scale framing is an important one because it changes the design constraints considerably. Skyler: When you think about CPO at the device level, the integration challenge is primarily about getting photonics onto or adjacent to a switch ASIC in a way that manages thermal coupling, fiber attach, and manufacturing yield. But when you scale up to a full rack — we're talking about top-of-rack switches, mid-tier aggregation, and potentially the spine layer — the CPO integration challenge becomes an infrastructure problem, not just a component problem. Skyler: The first challenge is fiber management. A 51.2 terabit switch with CPO might have thousands of individual fiber connections in a package that's far less accessible than a traditional pluggable faceplate. The fiber routing, bend radius management, and the physical assembly workflow all have to be rethought. Hyperscalers who are used to swapping pluggable optics in the field in minutes now have to think about what a CPO switch replacement looks like — it's a much more involved operation. Skyler: The second challenge is thermal management. Co-packaging puts the optical engine in much closer proximity to the switch ASIC, which is itself one of the hottest components in the rack. Silicon photonics performance is temperature-sensitive — laser wavelength, modulator efficiency, and detector responsivity all drift with temperature. Keeping the photonic layer cool enough to operate reliably when it's cheek-to-jowl with a 400-watt switch die requires careful package-level thermal design and potentially active thermal management on the optics side. Skyler: The third challenge, which the Electronics360 piece touches on, is the rack-level power distribution architecture. CPO switches change the power delivery profile relative to pluggable modules. With pluggable QSFP-DD or OSFP modules, the power is drawn through the faceplate and distributed to individual modules. With CPO, the optical power budget is integrated into the switch package power budget, which is already significant. You need power delivery network design that can handle both the peak demands of the ASIC and the steady-state optical power without creating noise that degrades signal quality. Skyler: Despite these challenges, the momentum toward rack-scale CPO is real. The power efficiency argument at scale is compelling — analysts have estimated that CPO can reduce the optical interconnect power by 30 to 50 percent compared to pluggable modules at equivalent bandwidth, and at the scale of a thousand-GPU cluster, that's a meaningful absolute power reduction. The Electronics360 piece frames this as an inflection point for rack-scale architecture, and I think that's right — we're moving from CPO being a component roadmap item to CPO being a system architecture consideration that affects how you design the whole rack. Skyler: The vendors who are going to win in rack-scale CPO are not just the photonics companies — they're the companies who can solve the system integration problem end to end: the package, the fiber management, the thermal solution, the rack power architecture, and the serviceability story. That's a much harder problem than it looks from the component level, and it's where I'd expect to see differentiation in the 2026-2028 timeframe as the first production deployments come online and the operators start figuring out what actually works in a live environment. Skyler: Alright, that's the show. Five stories, a lot of photons and a few electrons — turns out the future of A I fabric is probably both. CPO is coming, CPC is not going quietly, Meta wants open everything, Dell sees A I eating the datacenter, and there's a decade's worth of market maps being drawn right now by people betting on which