System-Level Design For 1.6 Tbps Interoperability In AI Data Centers - Semiconductor Engineering

Skyler: Welcome to Line Rate — the show tracking the chips, standards, and companies shaping datacenter fabric and A I high-speed interconnect. I'm Skyler Monroe, and if you're building, buying, or betting on the infrastructure that moves data at scale, this is your show. Thanks to our sponsors Ada, who helps enterprises actually integrate A I into their real workflows, and Zen Semiconductor, an umbrella company with a portfolio across the silicon industry. Alright — today we've got a packed episode: one point six terabit interoperability, the copper versus fiber war heating up in the CPO era, Synopsys dropping U E C and U A Link IP, a data center project in Italy running into a wall, and a look at how U.S. data centers are going off-grid to keep up. Let's get into it. Skyler: First up — Semiconductor Engineering has a deep-dive piece on system-level design for one point six terabit per second interoperability in A I data centers, and this one's worth unpacking carefully because it sits right at the intersection of where standards are written and where silicon actually has to work together. Skyler: So one point six terabits per second — that's where the industry is pointed right now for next-generation A I fabric ports. You're talking about eight hundred gig electrical lanes doubling up, or moving to higher-order signaling schemes that let you pack more bits through the same physical interface. The question that Semiconductor Engineering is really digging into here is not just can you reach one point six T on a single vendor's hardware — it's can two vendors' devices actually talk to each other at that speed without falling apart. Skyler: And that's a harder problem than it sounds. Interoperability at one point six T requires extremely tight coordination across the electrical interface, the SerDes, the retimer specs, the optical module specs, and the higher-layer protocol stack. Every one of those layers has tolerances that compound. So if your transmitter eye is slightly off, and the receiver equalization is tuned for a slightly different channel model, you can end up with a link that passes vendor A's internal tests and fails the moment you plug in vendor B's transceiver. Skyler: This is precisely the problem that efforts like the Ultra Ethernet Consortium are designed to solve — not just at the protocol layer but all the way down to the physical layer interoperability specs. U E C is still evolving. The spec is not fully ratified in all its layers, and that's important context. What we have right now is a framework with real momentum and real member buy-in from the hyperscalers and silicon houses, but the interoperability testing regimes, the plugfests, the conformance suites — those are still being built out. Skyler: What the Semiconductor Engineering piece highlights is that getting to one point six T interoperability isn't just a PHY problem. It's a system-level problem. You need to think about how the ASIC, the package, the PCB, the cable or optical module, and the far-end device all behave together as a system. That means co-simulation, that means channel modeling that accounts for insertion loss at higher baud rates, and that means agreeing on a reference channel model that vendors can actually design to. Skyler: For the people building A I clusters right now, this matters enormously. You're not buying a homogeneous rack from one vendor. You're integrating GPUs from one company, network switches from another, optical modules from a third, and cables from a fourth. If the interoperability story at one point six T isn't solid, you end up with integration hell at the exact moment you're trying to scale a multi-thousand GPU training cluster. So this work — unglamorous as it is — is absolutely load-bearing for the industry. Skyler: Story two — and this one's a bit of a detour from silicon, but it's directly relevant to anyone thinking about where A I infrastructure is actually going to get built. Plans for a one hundred twenty megawatt data center in Lombardy, Italy have been withdrawn. The reason? The municipality says they never received the data they needed to evaluate the grid connection. Skyler: Let that sink in for a second. One hundred twenty megawatts. That's a serious chunk of A I infrastructure capacity — not a hyperscale campus necessarily, but well into the range of a meaningful regional A I compute deployment. And it's dead in the water not because of permitting opposition, not because of a zoning fight, not because of water rights — but because the grid connection data didn't get submitted. Skyler: Now, you can read this a couple of ways. The cynical read is that this is a paperwork failure — somebody dropped the ball on the application and the municipality used it as a clean exit. The more structural read, which I think is probably closer to the truth given what we're seeing globally, is that grid operators and local governments are increasingly overwhelmed by the volume and scale of data center applications landing on their desks, and the process for evaluating large grid connections — especially in European markets with older grid infrastructure — is genuinely not keeping pace with demand. Skyler: Italy's grid situation is not unique. Across Europe, Ireland has been famously restrictive, the Netherlands has had moratoriums on new connections in certain regions, and the UK is dealing with multi-year queues for grid access. What's happening is that the appetite for A I compute is running directly into the physical and administrative limits of electrical infrastructure that was built for a very different era. Skyler: For the datacenter and interconnect community, the takeaway here is that the constraint on A I infrastructure scaling in 2025 and beyond is not going to be chip supply — at least not exclusively. It's going to be power. Where you can get it, how fast you can get connected, and what you have to do to secure it. Which leads nicely into our fifth story, but let's hold that thread. Skyler: What Lombardy illustrates specifically is that European expansion plans for A I data center capacity need to be stress-tested against power availability in a very literal, physical sense — not just modeled in a spreadsheet but validated with the actual grid operator. And that's a lesson that's relevant whether you're a hyperscaler siting a new campus or a colocation provider trying to attract an A I tenant. Skyler: Alright, story three — and this one is big if you're tracking the physical layer of A I interconnect. There's a detailed market analysis piece — sourced from a financial platform but with solid technical substance — asking the core question: is copper out and fiber in for A I data center connectivity? And how is the supply chain profit distribution shifting in the CPO era? Skyler: Let's start with the copper versus fiber question because it's more nuanced than the headline suggests. The short version is: copper isn't dead, but its addressable range in A I fabric is compressing. Direct attach copper — DAC cables — have been the dominant solution for short-reach connections inside a rack and between adjacent racks for years. They're cheap, they're passive, they don't need a transceiver with a laser and a detector, and at lower speeds they work great. Skyler: The problem is that as you scale to four hundred gig and eight hundred gig per lane, the signal loss on copper at meaningful distances becomes prohibitive. You either need active electrical cables with retimers — which add cost and power — or you move to optical. And at one point six T port speeds, the physics of copper for anything beyond very short distances gets really ugly. So what you're seeing is the crossover point — the distance at which optical becomes preferable — shrinking. Optical is winning at distances that copper used to own. Skyler: Now layer in co-packaged optics, which is really the centerpiece of this analysis. CPO means moving the optical engine off a pluggable module and directly onto the switch ASIC package. You eliminate the high-speed electrical interface between the ASIC and the optical module — which at one point six T is itself a massive source of signal integrity pain — and you replace it with a short optical waveguide or fiber attach right at the package edge. Skyler: The technical win from CPO is real: lower power, better signal integrity, the ability to drive longer optical reaches without heroic equalization. But the supply chain implications are profound. Right now, the pluggable transceiver market is a well-understood ecosystem. You've got module vendors, you've got the ASIC vendors, and the customer integrates them. With CPO, the optical engine is co-designed and co-packaged with the switch silicon. That means the module vendor and the ASIC vendor have to work together much earlier in the design cycle, and the value capture shifts. Skyler: Specifically, the analysis argues that CPO compresses margin for standalone pluggable module vendors and expands margin for companies that can integrate at the package level — which today is a short list. It also raises the integration risk and the qualification burden for customers. If a pluggable module fails, you swap it. If a CPO engine has an issue, you're looking at a much more complex situation. Skyler: For investors and supply chain architects: watch who has the packaging capability and the silicon photonics IP to play in CPO, and watch how the big switch ASIC vendors — your Broadcoms, your Marvelells — choose their optical partners. Those partnerships will define a big chunk of the A I fabric value chain for the next several years. Skyler: Story four — Synopsys has announced U E C and U A Link IP solutions targeting high-bandwidth A I accelerator clusters. This is a big deal for the ecosystem, even if it's not a headline-grabbing product launch. Let me explain why. Skyler: When a major EDA and IP vendor like Synopsys productizes an IP block for a given standard, it signals two things simultaneously. First, that the standard has matured enough that there's a real spec to implement against. Second, that the market demand is clear enough that Synopsys expects meaningful royalty and licensing revenue from fabless chip companies who will license this IP rather than build it themselves. Synopsys doesn't ship speculative IP. Skyler: So what are we talking about here technically? Ultra Ethernet — U E C — is the transport protocol layer being defined by the Ultra Ethernet Consortium, targeting A I training and inference fabrics. It's designed to be better than standard Ethernet for A I workloads in specific ways: lower latency, better handling of congestion in the all-to-all communication patterns that dominate large model training, and compatibility with existing Ethernet infrastructure investments. U A Link — U A Link — is the accelerator interconnect standard targeting scale-up fabrics, the high-bandwidth links that connect GPUs or A I accelerators within a node or a tightly coupled pod. Skyler: These are two different layers of the A I fabric stack. U E C handles scale-out — connecting across racks and pods. U A Link handles scale-up — connecting accelerators in tight proximity. And they're complementary, not competing. A full A I cluster architecture needs both. Skyler: What Synopsys shipping verified IP for both means is that a chip company designing an A I network chip or an accelerator ASIC can now license proven RTL for these interfaces rather than spending eighteen months building it from scratch. That compresses time to tape-out. It lowers risk. And it accelerates the ecosystem, because more chips with these interfaces means more chances for real-world interoperability testing, which feeds back into refining the standards. Skyler: The competitive angle: Synopsys is not alone in this space. Cadence and Rambus also have IP businesses that will be targeting the same sockets. Watch for similar announcements from them. But being first to market with qualified IP for an emerging standard is a meaningful advantage — it's hard to displace an IP block that's already in a customer's design when tape-out is two months away. Skyler: One caveat worth holding onto: U E C spec work is still ongoing in some areas, and IP that ships today may need updates as the spec finalizes. That's normal in this industry, but it means customers licensing this IP need to understand the versioning story and what their upgrade path looks like if the spec moves. Skyler: Last story — and we're picking up the power thread from the Italy story earlier. Data Center Dynamics has a piece on how U.S. data centers are turning to behind-the-meter power as grid constraints intensify, featuring David Bosco from PROPWR, which is a company focused on alternative power procurement for data centers. Skyler: Behind-the-meter power — let's define that quickly. The "meter" here is the utility interconnection point. Behind-the-meter means you're generating or procuring power on your side of that connection — think on-site gas generation, solar plus storage, fuel cells, or arrangements where you're co-located with a generation asset. You're not relying solely on the utility to deliver electrons to your facility. Skyler: Why does this matter for A I infrastructure specifically? Because A I compute clusters are power-hungry in a very concentrated way. A single A I training pod can draw tens of megawatts. A hyperscale A I campus can push into the hundreds of megawatts — as we just saw with that Lombardy project. The grid, in many markets, simply cannot accommodate that demand on the timescales that A I infrastructure buildout requires. Grid interconnection queues in the U.S. are running years long in many ISOs. That's not compatible with a hyperscaler that wants to have capacity online in eighteen months. Skyler: Behind-the-meter generation is one of the practical answers to that problem. You contract with a power developer — like a PROPWR — who builds and operates generation capacity co-located with or adjacent to your data center, and you are not waiting in the utility interconnection queue for your full load. You might still need a grid connection for redundancy or for supplemental power, but your primary load is served from a source you control. Skyler: The implications for the fabric and interconnect community are more indirect but real. If A I data center buildout is constrained by power access in traditional colocation markets — and it is — then the next generation of large-scale A I clusters may end up in locations that are driven by power availability rather than traditional datacenter geography. That means connectivity infrastructure — fiber, dark fiber, long-haul optical — becomes a critical consideration because you're potentially siting a massive compute cluster in a location that wasn't previously a networking hub. Skyler: It also means the inside-the-datacenter fabric story doesn't change — your NVLink, your U A Link, your U E C scale-out fabric still have to perform — but the where of these deployments is increasingly being driven by a power map rather than a real estate map. For anyone designing or selling into A I infrastructure, that's worth factoring into your go-to-market. Skyler: The PROPWR angle specifically highlights a growing category of companies that are essentially power infrastructure developers who are purpose-building for data centers. It's a space that's attracting serious capital because the constraint is real and the demand is enormous. Expect to see more of these names in the news as hyperscalers and even large enterprises try to derisk their A I compute buildouts from power uncertainty. Skyler: That's a wrap on today's episode of Line Rate. We covered one point six T interoperability and why the system-level design work is as important as the silicon, a power-related project withdrawal in Italy that illustrates the real constraint on A I infrastructure scaling, the copper-to-fiber transition and how CPO is reshaping the supply chain, Synopsys shipping U E C and U A Link IP which is a genuine ecosystem accelerant, and the behind-the-meter power story that's changing where A I compute actually gets built. Line Rate, brought to you by Ada and Zen Semiconductor — Ada helps organizations integrate A I into their real workflows, and Zen Semiconductor is an umbrella company with a portfolio of companies across the silicon industry. If you found this useful, please subscribe and share it with someone building or investing in A I infrastructure. Show notes with links to all the sources are available wherever you're listening. See you next time.