The Battle for AI Data Center Connectivity: Is Copper Out and Fiber In? How Are Supply Chain Profit Distributions Changing in the CPO Era? - Moomoo

Skyler: Welcome to Line Rate — the show tracking the chips, standards, and companies shaping A I datacenter fabric and high-speed interconnect. I'm Skyler Monroe, and if it moves data between GPUs, across racks, or between datacenters, we're covering it. Big thanks to our sponsors: Ada, which helps clients integrate A I into their workflows, and Zen Semiconductor, an umbrella company with a portfolio of businesses across the silicon industry, with Ada as part of that family. Alright — today we've got a packed episode. We're talking about whether copper is actually dead in the A I datacenter, photonic chips going mainstream, a 3.4 million dollar optics deal between Sivers and SemiNex, Broadcom's new Tomahawk Ultra switch, and Cisco's argument that the future of A I is distributed across datacenters, not concentrated in one. Let's get into it. Skyler: First up — the copper versus fiber debate, and what co-packaged optics is doing to the supply chain economics in A I datacenters. This one's been simmering for a while, but it's reaching a boil. Here's the short version: the A I datacenter is fundamentally different from the cloud compute datacenter it's replacing. GPU clusters doing large-scale training need enormous bisection bandwidth at very low latency, and the distances inside modern A I pods — especially as they scale to tens of thousands of GPUs — are pushing past what passive copper can reliably do. Skyler: For a long time, direct attach copper, or DAC cables, were the default inside a rack. They're cheap, they're passive, they work great at short distances. Active electrical cables extended that a bit. But once you're crossing racks, or connecting spine switches in a fat-tree or dragonfly topology, the signal integrity constraints get brutal. At 800 gigabits per second per lane, which is where the industry is heading, copper just starts losing. The physics aren't on its side. Skyler: So fiber is winning more of that territory — and the question isn't really "if" anymore, it's "how fast" and "at what layer of the stack." That's where co-packaged optics, CPO, becomes the really interesting inflection point. CPO means moving the optical transceiver from a pluggable module on the faceplate of a switch into the same package as the switching ASIC. You're putting the photonics right next to the silicon, which cuts the electrical path between the chip and the optical interface dramatically. Skyler: Why does that matter? Because that short electrical path is where you lose signal, burn power, and add latency. A pluggable transceiver sitting at the faceplate of a 512-port switch is connected to the ASIC by a long trace on the PCB. At 100-plus gigabits per lane, that's a real engineering problem. CPO eliminates most of that problem by design. Skyler: But here's what's really shifting: the supply chain profit distribution. In the pluggable optics world, the transceiver vendors — companies like II-VI, Coherent, Inphi, Lumentum — capture a big chunk of the margin. The switch vendor buys transceivers and integrates them. In the CPO world, the boundary between "switch" and "optic" dissolves. The ASIC vendor, the photonic integrated circuit vendor, and the substrate and packaging house all become co-dependent in a way they weren't before. Margin shifts. Who owns the customer relationship shifts. It's a genuine supply chain restructuring, and it's happening right now. Skyler: Hyperscalers are paying close attention because CPO could meaningfully reduce power consumption per bit — estimates range from 30 to 50 percent improvement in optical I/O power efficiency — and at the scale of a hundred-thousand-GPU cluster, that is not a rounding error. So no, copper isn't "out" universally — it's still the right answer inside a rack at current speeds — but fiber is winning the rack-to-rack and beyond battle, and CPO is the technology that makes that economical at scale. Skyler: Next story: photonic chips going mainstream. Intelligent Living ran a piece arguing that silicon photonics is crossing the chasm — first in datacenter networking, and eventually in compute itself. Let's unpack that, because there are two really different claims bundled together there and they deserve separate treatment. Skyler: On the networking side, silicon photonics is already mainstream in the sense that it underpins a huge fraction of the coherent and short-reach optics shipping into datacenters today. Companies like Intel, Cisco, Marvell, and a bunch of pure-play photonics startups are all fabbing photonic integrated circuits on silicon or silicon-on-insulator platforms. The integration of waveguides, modulators, and photodetectors on a chip — using processes adjacent to standard CMOS — is a proven manufacturing approach at this point. Skyler: What's newer is the push toward higher levels of integration. We're talking about combining lasers, modulators, and drivers on a single die or in a tightly integrated multi-chip module. The laser part has historically been the hard part for silicon photonics, because silicon is a lousy light emitter. Most approaches either use external lasers coupled in, or heterogeneous integration of III-V materials — think indium phosphide — bonded to a silicon photonic die. Both approaches are maturing, and the yields are getting to where you can make a real business case. Skyler: For A I fabric specifically, the exciting angle is that silicon photonics could enable ultra-high-density optical I/O on switch ASICs and eventually on GPU packages themselves. If you can get, say, a terabit per second of optical I/O on a small-form-factor chip with competitive power efficiency, you've fundamentally changed what's possible for scale-up interconnect. That's the CPO thesis, and silicon photonics is the technology that makes CPO manufacturable at cost. Skyler: Now the second claim — photonics in compute — is much further out and frankly much more speculative. The idea is that optical interconnects inside a chip, or between chiplets, could solve the memory bandwidth and chip-to-chip latency problems that are currently bottlenecks for A I accelerators. There are research programs at all the major players exploring this. But the manufacturing integration challenges are enormous. You're talking about getting optical components onto or adjacent to a logic die that's running at extremely high power densities. Thermal management alone is a nightmare. I'd put this at a ten-year horizon minimum for production systems. Worth watching, not worth pricing into your roadmap today. Skyler: Alright, story three: Sivers Semiconductors and SemiNex have signed a 3.4 million dollar program to develop laser components for A I datacenter optics. This is a smaller deal in dollar terms, but it's a really instructive example of how the ecosystem is building out underneath the big headline companies. Skyler: Sivers is a Swedish company that does compound semiconductor work — they have RF and photonics divisions, and on the photonics side they're focused on edge-emitting lasers and related components. SemiNex is a Massachusetts-based company that specializes in high-power semiconductor lasers. Together, this program is targeting the laser source problem I just mentioned in the photonics story. Skyler: Here's the context: as silicon photonics platforms push toward higher speeds and higher port counts, the laser source is a critical supply chain dependency. Most silicon photonic transceivers today use external cavity lasers, often indium phosphide based, that are fiber-coupled into the silicon photonic chip. That coupling is a yield and cost challenge. The industry is actively working on better approaches — whether that's improved butt-coupling, flip-chip bonding of laser dies onto silicon photonic wafers, or developing new laser structures that are more compatible with silicon photonic manufacturing. Skyler: A 3.4 million dollar program is seed-level in the context of what it takes to develop and qualify a new laser component for a hyperscaler supply chain. But it tells you something important: there is active investment at every layer of the photonics stack, not just at the big tier-one suppliers. The laser source, the modulator, the photodetector, the driver IC, the DSP — each of these is a specialization, and there are focused companies working each angle. Skyler: For investors and supply chain teams watching this space, the Sivers-SemiNex deal is a signal that the ecosystem is deepening. When you see compound semiconductor specialists partnering specifically around datacenter A I optics applications, that's the market pulling investment toward the components that are actually bottlenecked. And right now, high-efficiency, high-reliability laser sources that can meet the thermal and integration requirements of CPO are genuinely bottlenecked. Skyler: What I'll be watching is whether this program leads toward a specific CPO-targeted laser product, or whether it's more of a capabilities development effort. The path from a research program to a qualified component in a hyperscaler supply chain is long and expensive. But the direction is right, and it's good to see European and North American compound semiconductor expertise being pointed directly at this problem. Skyler: Story four: Broadcom has announced the Tomahawk Ultra, and this one is worth spending some time on because Broadcom doesn't announce new merchant silicon switch ASICs casually. The Tomahawk line is the industry benchmark for high-radix Ethernet switching, and each generation has set the pace for what's possible in terms of port density, bandwidth, and power efficiency. Skyler: The Tomahawk Ultra is targeting HPC and A I workloads specifically, with an emphasis on low latency. Broadcom is citing capabilities relevant to emerging low-latency Ethernet standards — which is interesting timing given where the Ultra Ethernet Consortium, the U E C, is in its standardization work. The U E C is working on Ethernet enhancements specifically for A I training traffic — things like better multipath load balancing, improved congestion notification, and transport-layer features that close the gap with InfiniBand for all-reduce and collective communication patterns. Skyler: Now, to be clear, Tomahawk Ultra is shipping as an Ethernet switch ASIC. It's not a U E C certified product, because U E C specs are still being finalized. But Broadcom is clearly positioning this chip to be the hardware substrate that U E C deployments run on when those specs land. That's a smart play — get the hardware into production and qualified in customer systems, and then layer the software and protocol features on top as the standard matures. Skyler: On the raw numbers: Broadcom is pushing aggregate switch bandwidth into the multiple-petabit-per-second range with Tomahawk Ultra. The per-port speeds are scaling with the 800G and 1.6T Ethernet roadmap. The latency improvements come from a combination of faster internal pipeline stages and, critically, from how the chip handles elephant flows and congestion in A I collective communication patterns. Skyler: Why does latency matter so much for A I training? Because in a large GPU cluster running distributed training, the all-reduce collective — where every GPU has to exchange gradient information with every other GPU — is in the critical path of the training step. If your network adds even microseconds of jitter on that operation, it multiplies across thousands of GPUs and you end up with GPUs stalling waiting for network I/O. That's wasted A I compute, and at the cost of H100 or B200 time, that is extremely expensive waste. Skyler: The competitive context here is InfiniBand, which has historically dominated A I training clusters because NVIDIA built NCCL and its collective communication library specifically to leverage InfiniBand's RDMA and hardware offload capabilities. Broadcom's bet, and the U E C's bet more broadly, is that enhanced Ethernet can close that latency and collective-efficiency gap while offering the cost and ecosystem advantages of standard Ethernet. Tomahawk Ultra is Broadcom putting serious hardware credibility behind that bet. Skyler: The other angle worth noting: Tomahawk Ultra is merchant silicon, which means any whitebox switch vendor or ODM can build a switch around it. That's a direct challenge to NVIDIA's Quantum InfiniBand switches, which are vertically integrated. If the performance gap closes, procurement teams at hyperscalers and large enterprises have a much easier time justifying Ethernet — and that is a very large market share shift opportunity. Skyler: Last story today: Cisco published a blog arguing that the future of distributed A I isn't concentrated in a single datacenter — what they're calling "scale-across." This is less about a specific chip or standard and more about a strategic framing that I think is worth taking seriously, because it has real implications for interconnect architecture. Skyler: The core argument is this: A I training clusters are getting so large that building them all in one location is increasingly impractical. Power constraints, land availability, cooling infrastructure, and frankly the lead times on utility grid connections mean that the largest A I deployments of the next few years are going to span multiple sites. That's not a new observation — hyperscalers have been multi-site for years — but the implication for A I fabric is new. Skyler: Training a frontier model across multiple datacenters separated by real distance changes your interconnect constraints fundamentally. Inside a single datacenter, you're dealing with hundreds of nanoseconds of latency over optical or copper fabric. Across datacenters connected by dark fiber or leased wavelengths, you're dealing with milliseconds — sometimes tens of milliseconds depending on distance. That's three to four orders of magnitude worse, and collective communication algorithms that work fine inside a datacenter break down or require fundamental redesign at those latencies. Skyler: The approaches being explored for scale-across training are interesting. One is to redesign the training parallelism strategy so that the communication patterns that need to be fast — like all-reduce for gradient synchronization — happen within a single site, while the slower inter-site communication handles pipeline stages or model parallelism slices where you can tolerate higher latency. This requires very careful partitioning of the model and the compute graph. Skyler: Another approach is to invest in extremely high-bandwidth inter-datacenter links. If you can get multi-terabit-per-second coherent DWDM capacity between sites, you can potentially tolerate the latency by increasing the batch size of data you move in each transfer, amortizing the round-trip latency over a larger payload. That's essentially trading latency sensitivity for bandwidth efficiency, which works for some training workloads but not all. Skyler: Cisco's angle here is that they have both the routing and optical transport portfolio to be the inter-datacenter fabric vendor for this use case — and that's a credible position. Connecting datacenters at scale is exactly what routers and coherent DWDM systems are built for. The interesting question is whether A I-specific requirements — deterministic latency, ultra-low jitter, high-bandwidth multicast for model distribution — push the inter-datacenter fabric to need new features, or whether existing carrier-grade infrastructure is good enough. Skyler: My read is that it's both. For some workloads, like inference serving, existing WAN infrastructure is totally adequate. For frontier model training at the largest scales, you're going to need purpose-built inter-datacenter fabric with much tighter latency bounds and traffic engineering than a standard IP/MPLS network provides. That's a new product opportunity, and not just for Cisco — it's an opportunity for anyone who can deliver deterministic, high-bandwidth, low-latency inter-datacenter connectivity. Watch this space closely over the next two years, because the market is going to develop fast. Skyler: And that is a wrap on today's episode of Line Rate. We covered a lot of ground — the copper-to-fiber transition and what CPO is doing to supply chain economics, silicon photonics going mainstream in networking, the Sivers and SemiNex laser program, Broadcom's Tomahawk Ultra and what it means for the U E C ecosystem, and Cisco's scale-across thesis for distributed A I training. If you work in silicon, networking, or datacenter architecture, I hope this gave you something useful to chew on. Line Rate is brought to you by Ada and Zen Semiconductor — Ada helps clients integrate A I into their workflows, and Zen Semiconductor is an umbrella company with a portfolio of businesses across the silicon industry. If you found this episode useful, please subscribe and share it with someone who's thinking hard about A I infrastructure. Show notes with links to all the stories we covered today are on the website. I'll see you next time.