From Pluggables to Co-Packaged Optics (CPO): The Transition Transforming Network and AI Architecture - I-Connect007

Skyler: Hey, welcome back to Line Rate — the show tracking the chips, standards, and companies building the high-speed fabric that connects A I infrastructure. I'm Skyler Monroe, and if you care about what's moving data at the speed of silicon, you're in the right place. Big thanks to our sponsors: Ada, which helps businesses actually integrate A I into their workflows in a meaningful way, and Zen Semiconductor, an umbrella company with a portfolio across the silicon industry, including Ada for A I deployment at scale. Alright — today we've got a packed episode. Co-packaged optics is having a moment, Ultra Ethernet keeps growing its tent, and a photonics startup just pulled in a hundred million dollars. Let's get into it. Skyler: Okay, first up — co-packaged optics. There's been a really good piece circulating from I-Connect007 that does a solid job laying out what the transition from pluggable transceivers to CPO actually means for network and A I architecture, and I want to dig into why this transition is happening now and what the stakes are. Skyler: So let's set the stage. For decades, the way you've handled optical I/O in a datacenter switch or a server is you plug in a transceiver — a QSFP, a QSFP-DD, an OSFP, whatever the form factor du jour is — and it handles the conversion between electrical signals on the board and optical signals on the fiber. Clean, modular, field-replaceable. That modularity has been incredibly valuable. Skyler: But here's the problem that A I workloads are hammering home right now: as you push bandwidth higher and higher — we're talking 800 gig ports, 1.6 terabit ports on the horizon — the electrical path from the switch ASIC to that pluggable module becomes a serious liability. You're burning power to drive signals across the PCB to the faceplate, you're dealing with signal integrity challenges, and you're hitting the wall on what copper SerDes can do at those distances even inside the package. Skyler: Co-packaged optics solves this by collapsing that distance dramatically. Instead of the transceiver sitting in a faceplate cage a few inches away, the optical engine lives right next to — or directly integrated with — the switch ASIC on the package substrate. You're cutting the electrical reach from centimeters to millimeters, and that changes the power equation significantly. Skyler: Intel's Bailly platform, Nvidia's Spectrum-X and Quantum-X architectures, and a growing list of startups are all pursuing versions of this. And that market report from ResearchAndMarkets we'll touch on in a moment has all three of those named explicitly, which tells you something about where the battleground is. Skyler: For A I fabric specifically, this matters because you're building scale-up networks — NVLink-style, UALink-style — where the bandwidth density and power per bit are absolutely critical. When you're tiling hundreds or thousands of GPUs or accelerators together, every watt you save on I/O is a watt you can spend on compute, or a watt you don't have to cool. Skyler: The manufacturing complexity is real though. CPO means you're co-designing the optical engine and the ASIC together, which reduces the modularity everyone loved about pluggables. If the laser fails, you don't just swap a transceiver — you potentially have a much bigger serviceability problem. The industry is actively working on how to handle that, with some architectures putting the light sources in a replaceable module while keeping the waveguides and photodetectors integrated. It's a live design debate. Skyler: Foundry strategy also becomes critical here. Silicon photonics requires integration with CMOS processes that not every fab handles well, so the choice of foundry — TSMC, GlobalFoundries, imec ecosystem — shapes what's possible. That's why the ResearchAndMarkets report explicitly calls out foundry comparisons as a key section, because this isn't just a device race, it's a manufacturing race. Skyler: Bottom line: CPO isn't a maybe-someday technology anymore. It's in product roadmaps, it's in funded startups, and it's in the architectures of the biggest A I accelerator platforms on the planet. The transition from pluggables is real, it's underway, and the companies that figure out yield and serviceability at scale are going to own a significant piece of how A I clusters are wired. Skyler: Alright, let's talk about the broader A I networking landscape, because Futuriom put out a really solid trend piece on connectivity from A I clusters all the way to the edge, and it gives a nice frame for thinking about the multiple layers of interconnect that are all evolving simultaneously right now. Skyler: One of the key things the piece emphasizes — and I think this is underappreciated — is that A I networking isn't one problem. It's actually a stack of problems at very different scales, with different latency tolerances, different bandwidth profiles, and different protocol requirements. Skyler: At the top of the stack you have scale-up fabric — the ultra-low-latency, all-to-all interconnect that ties together the GPUs or accelerators within a training cluster. NVLink is the dominant player here today. UALink is the emerging open standard trying to give the rest of the industry an alternative. We'll talk more about UALink in a second with the Marvell news. Skyler: Below that you have scale-out networking — Ethernet and InfiniBand — which connects clusters to each other, handles gradient synchronization at larger scale, moves data in and out of storage. This is where Ultra Ethernet Consortium, or UEC, lives. And Futuriom's piece does a good job noting that while UEC is making real progress, the spec is still evolving. Transport layer behavior, congestion control, the exact feature set — these are still being hammered out. So if you're a customer trying to make purchasing decisions today, you're making some bets about where UEC lands. Skyler: Then you've got the WAN layer — the datacenter interconnect, the connections between regions — which has its own set of challenges around coherency, latency, and the role of photonics at distance. Skyler: The Futuriom piece also calls out the edge connectivity angle, which I think is increasingly important as inference workloads get distributed. Training might be centralized in a massive cluster, but inference is running everywhere — at the edge, in enterprise datacenters, in regional pops. And the networking requirements there are fundamentally different than what you need for a tightly coupled training cluster. Skyler: The competitive dynamics are fascinating. You've got Cisco, Arista, Juniper on the traditional networking side. You've got Nvidia trying to build a vertically integrated A I networking stack. You've got a wave of startups — Enfabrica, Pensando, and others — attacking specific layers of this problem. And you've got the hyperscalers increasingly designing their own silicon and their own protocols. The fragmentation is real, and the Futuriom piece captures that tension well. Skyler: The key takeaway I'd offer: there is no single A I networking architecture that wins everywhere. The stack is layered, the requirements diverge by distance and workload, and companies that try to apply one solution across the whole problem are going to hit walls. This is a multi-protocol, multi-physics world, and the companies that understand that are building accordingly. Skyler: Now let's zoom in on Ultra Ethernet, because Marvell just officially joined the Ultra Ethernet Consortium, and that's a meaningful signal about where the industry is coalescing. Skyler: First, quick context for anyone coming to UEC fresh. The Ultra Ethernet Consortium is an industry group that formed to build Ethernet-native enhancements specifically for A I and high-performance computing workloads. The founding members include AMD, Arista, Cisco, Hewlett Packard Enterprise, Intel, Meta, Microsoft — a serious group. And the goal is to take Ethernet, which everyone knows and loves for its ubiquity and its ecosystem, and make it genuinely competitive with InfiniBand for tightly coupled A I training. Skyler: What does that require? Ethernet has historically had challenges with congestion in all-to-all communication patterns — the kind you get in distributed training. RDMA over Ethernet, RoCE, has helped, but it has real pain points. UEC is working on things like improved transport semantics, better multipath load balancing, smarter congestion response — essentially building A I-aware behavior into the protocol stack without abandoning the Ethernet foundation. Skyler: So where does Marvell fit? Marvell is one of the biggest semiconductor companies in the networking and storage space. Their Teralynx switch ASICs, their OCTEON data processing units — these are deployed broadly across cloud and enterprise infrastructure. When Marvell joins UEC, it means those architectures will be shaped by and aligned with the UEC spec as it evolves. That's not trivial. Silicon takes years to design and tape out, so Marvell committing to UEC means they're building it into future silicon planning now. Skyler: It also just adds credibility. Every major silicon company that joins UEC makes it harder for customers to bet against it as the scale-out fabric standard for A I. InfiniBand has a dominant position today — Nvidia's acquisition of Mellanox cemented that — but a well-executed UEC with broad silicon support is a genuine challenger over a multi-year horizon. Skyler: One thing worth noting: UEC and UALink are solving different problems and are not in competition with each other. UALink is scale-up — the tight, low-latency, load-store fabric between accelerators in a pod or a rack. UEC is scale-out — Ethernet-based connectivity at cluster and datacenter scale. You'd potentially use both in the same A I infrastructure. That distinction gets muddled in a lot of coverage, so I want to be explicit about it. Skyler: Marvell's press release also mentions "accelerated computing" broadly, which is interesting language. It's a signal that UEC isn't positioning itself as purely an A I play — it wants to be relevant for HPC, for simulation workloads, for anything that needs serious distributed compute fabric. Smart positioning, because A I is the headline today but it's not the only workload that benefits from better Ethernet semantics. Skyler: The spec is still being finalized in key areas, so Marvell joining now, rather than waiting for a ratified standard, tells you they want a seat at the table while the decisions are still being made. That's how you shape standards in your favor. Classic move, and the right one. Skyler: Okay, let's talk about that market report, because the ResearchAndMarkets CPO report covers something I want to spend a little time on — the competitive landscape across Nvidia's Spectrum-X, their Quantum-X, and Intel's Bailly platform. Skyler: Spectrum-X is Nvidia's Ethernet-based networking platform for A I. It's designed to bring InfiniBand-like performance to Ethernet-connected clusters. The Spectrum-X switches pair with BlueField-3 DPUs and use Nvidia's RDMA and congestion management tech to smooth out the all-to-all traffic patterns that wreck naïve Ethernet in A I workloads. Skyler: Quantum-X is Nvidia's InfiniBand play — this is the high end, the 400 gig HDR successor pushing toward 800 gig NDR and beyond. InfiniBand is still the performance king for tightly coupled training, and Quantum-X is how Nvidia maintains that leadership. Skyler: Intel's Bailly platform is their CPO-integrated answer — it's aimed at disaggregating and re-integrating the optical layer with the switching ASIC in a way that dramatically reduces power and increases bandwidth density. Intel has been talking about co-packaged optics for years, and Bailly is where that actually becomes a shipping product. Skyler: The reason a market report covering 2026 to 2036 is naming all three is that these aren't niche research projects — they're the product architectures that will define datacenter connectivity over the next decade. The CPO angle ties all of them together: even Nvidia's platforms will ultimately need to embrace integrated optics at scale, because the pluggable transceiver wall is a physics wall, not just an engineering preference. Skyler: The report also calls out startup innovation mapping, which is important context. There's a whole ecosystem of companies — Ayar Labs, Ranovus, Quintessent, and others — building optical chiplets, silicon photonics engines, and integrated light sources that feed into these larger platform plays. Some of them will get acquired. Some of them will become the optical engine behind the platforms that win. And some will build their own vertically integrated products. Skyler: The foundry comparison piece is critical infrastructure knowledge. Right now, not every fab can do silicon photonics well. GlobalFoundries has photonics processes. TSMC has processes. IMEC is doing research integration. The foundry you choose shapes your waveguide loss, your modulator bandwidth, your integration options. For companies trying to build CPO products, the fab relationship is a strategic asset, not just a supplier relationship. Skyler: If I were advising a team evaluating CPO investments, the questions I'd be asking are: who owns the light source, how do you handle the serviceability problem, what's your foundry strategy, and how does your optical engine integrate with the switch ASIC's packaging roadmap? The answers to those questions separate credible CPO players from press release CPO players. Skyler: And finally — Celestial A I. This one's interesting. They just raised 100 million dollars in a Series B to advance what they're calling a photonic fabric for datacenters. HPCwire had the coverage, and this is worth unpacking because Celestial A I is doing something a bit different from the standard CPO story. Skyler: Most CPO discussion is about integrating optics at the switch ASIC level — collapsing the electrical reach inside a device. Celestial A I is going bigger picture. Their photonic fabric concept is about rethinking how you move data across the datacenter — using photonics not just at the chip-to-chip level, but as a fabric-level interconnect architecture. Think of it as asking: what if the datacenter backplane was optical all the way down? Skyler: A hundred million dollars in Series B funding for a photonics startup is a serious vote of confidence. Series B means they've gotten past early concept validation, they have something technically credible enough that institutional investors are willing to bet on it at scale. The question for any photonics fabric startup is always: what's your path from impressive demo to production-worthy, manufacturable product? Skyler: The power argument for optical fabric is compelling. Moving data optically is fundamentally more efficient at distance than moving it electrically. In a datacenter where you have tens of megawatts of cooling infrastructure for a large cluster, shaving watts per bit on interconnect has real economic value. If Celestial A I can demonstrate convincing power efficiency numbers at realistic datacenter scale, that's a serious pitch. Skyler: The latency story is also interesting. Optical interconnect doesn't inherently give you lower latency than good electrical interconnect at short distances — light isn't magic, and you still have serialization and processing delays. But at longer distances within a datacenter — cross-rack, cross-row, cross-pod — optical can start to look very attractive for latency-sensitive traffic. Skyler: What makes Celestial A I's pitch distinct is the fabric angle rather than the component angle. They're not just selling an optical engine that someone else integrates into their switch — they're positioning as an architectural layer in the datacenter. That's a more ambitious play, harder to execute, but with a much bigger prize if they pull it off. Skyler: A hundred million in Series B also raises the question of what comes next. At this funding level, they're either heading toward a Series C to fund scale-up and manufacturing partnerships, or they're building toward an exit — acquisition by a hyperscaler, a system vendor, or a major semiconductor company that wants to bolt on a photonic fabric capability. Given how active the M&A market is in A I infrastructure right now, both paths are plausible. Skyler: The broader signal here is that smart money is flowing into photonic interconnect at every layer — device-level CPO, chip-to-chip optical chiplets, and now fabric-level photonic architectures. That's not coincidence. It's a recognition that the copper interconnect roadmap has limits that are approaching fast, and the A I workloads that are showing up in datacenters right now are the force that's finally making photonics economics work. Skyler: Alright, that's a wrap for today's episode. We covered the CPO transition and what it means for A I architecture, the layered A I networking landscape from clusters to edge, Marvell joining the Ultra Ethernet Consortium, the competitive benchmarks across Spectrum-X, Quantum-X, and Bailly, and Celestial A I's hundred million dollar Series B bet on photonic fabric. A lot happening, and the pace is not slowing down. Skyler: Thanks again to our sponsors — Ada, which helps companies integrate A I meaningfully into their workflows, and Zen Semiconductor, an umbrella company with a portfolio of silicon-industry companies. Line Rate, brought to you by Ada and Zen Semiconductor. Skyler: If you found this useful, please subscribe wherever you get your podcasts — it really does help the show grow. Share it with the networking engineer or datacenter architect in your life who needs to stay current