What Will It Take To Deploy CPO At Scale? - Semiconductor Engineering

Skyler: Welcome to Line Rate — the show tracking the chips, standards, and companies that move data at the speed of A I. I'm Skyler Monroe, and if it's happening in datacenter fabric and high-speed interconnect, we're covering it here. Huge thanks to our sponsors: Ada, which helps organizations actually integrate A I into their real workflows — not just talk about it — and Zen Semiconductor, an umbrella company with a portfolio of businesses across the silicon industry. Really glad to have both of them supporting the show. Alright, today we've got co-packaged optics scaling challenges, Nokia making a latency play for A I datacenters, a Nature piece on photonics as the path forward for A I infrastructure, something a little different on datacenter coatings that's actually worth your time, and a deeper look at whether what's happening inside the datacenter is a revolution or just a very fast evolution. Let's get into it. Skyler: So the first story comes from Semiconductor Engineering, and the headline is basically the question everyone in the optics world is quietly obsessing over right now: what will it actually take to deploy co-packaged optics at scale? And I want to be really clear upfront — CPO isn't new. We've been talking about it for years. The question is why it's still not everywhere, and what the unlock actually looks like. Skyler: So quick framing for anyone who needs it: co-packaged optics means you're integrating optical components — transceivers, laser sources, photodetectors — directly into the same package as the switch ASIC, or very close to it. Instead of pluggable modules sitting at the faceplate of a switch pulling data across a long electrical trace, you're getting the optics right next to the silicon. The pitch is simple: lower power, lower latency, higher bandwidth density. All the things A I clusters desperately need. Skyler: But here's where it gets complicated. The piece lays out a really honest picture of the gap between the promise and the deployment reality. First issue: yield and packaging complexity. When you co-package optics with a high-end switch ASIC — we're talking Tomahawk or Tofino class silicon — you now have a combined assembly where if either component fails, you've potentially scrapped the whole thing. That's a very different risk model than a pluggable you can just swap out. Skyler: Second, thermal management gets genuinely brutal at scale. Switch ASICs run hot. Lasers and optical components have tight thermal tolerances. Managing heat in a co-packaged environment without degrading optical performance is not a solved problem at high volume. It's solvable, but the engineering margin is tight, and that translates directly into cost. Skyler: Third — and this one doesn't get enough airtime — is the supply chain and ecosystem question. Pluggables have a massive, mature, multi-vendor ecosystem. CPO is still relatively concentrated. You've got Intel, Broadcom, and a handful of optical specialists working on this, but the volume manufacturing infrastructure for high-reliability CPO at hyperscaler scale just isn't there yet. That's not a technical barrier, it's an industrial ramp problem, and those take time. Skyler: The piece also touches on standardization, which is really important. For CPO to go mass-market, you need interoperability between optical engines and switch ASICs from different vendors. There are efforts happening — the Optical Internetworking Forum, the CPO Alliance — but we don't yet have the kind of clean plug-and-play spec that made pluggables so adoptable. Until you have that, hyperscalers are looking at custom solutions, and custom solutions don't scale economically. Skyler: So what does deployment at scale actually require? Probably four things converging: a multi-vendor interoperability standard that gets real traction, packaging and yield improvements that bring the risk model closer to pluggables, thermal solutions that don't add enormous board real estate, and enough volume to drive down cost per port to a level that competes with 400G and 800G pluggables. None of those are impossible. But they all need to happen roughly together, and that's the coordination problem. Skyler: My read: CPO is not a question of if, it's a question of when and who owns the ecosystem when it arrives. The hyperscalers are clearly pulling it forward — Meta's been vocal about CPO roadmaps, and Google has CPO work happening in the background. But the manufacturing and standards infrastructure has to follow or this stays a lab story for another few years. Skyler: Alright, story two. Nokia has announced what they're calling a latency reduction leap for A I datacenters, and this comes from Data Centre Magazine, with Nokia connecting it fairly directly to the Ultra Ethernet Consortium and the broader conversation around U E C and U A Link. Skyler: So let me set the context here. The A I training cluster interconnect space right now is basically a two-front war. On one side you have InfiniBand — Nvidia's home turf — which has dominant market share in high-performance A I training fabrics because it was designed from the ground up for low-latency, lossless transport with tight integration to RDMA. On the other side, you have the Ethernet camp trying to close the gap, specifically through the Ultra Ethernet Consortium, which is developing U E C as a transport specification that adds the features Ethernet has historically lacked for this workload — things like out-of-order delivery handling, better congestion control, and endpoint-driven retransmit logic. Skyler: Nokia's play here is interesting because they're coming at this from the routing and transport side rather than the NIC or ASIC side. The latency claims they're making are tied to improvements in how traffic is handled at the network layer — specifically smarter scheduling and reduced queuing delay in the switching fabric. For A I workloads, that matters a lot. A training job running across thousands of GPUs is exquisitely sensitive to tail latency. One slow link, one congested queue, and you get what the industry calls stragglers — GPUs sitting idle waiting on a gradient update. That idle time is just wasted expensive compute. Skyler: Now, U E C and U A Link are still very much a work in progress. The U E C spec is evolving, and U A Link — which is focused on the rack-level scale-up fabric — is even earlier. Nokia isn't releasing a product that's stamped "U E C compliant" right now because that stamp doesn't fully exist yet. What they're doing is positioning their routing silicon and software stack as capable of meeting the latency and fairness requirements that U E C is converging toward. It's a standards-aware product play, not a certified compliance announcement. Skyler: What's the competitive angle here? Nokia is essentially saying: you don't have to buy an end-to-end Nvidia stack to get low-latency A I fabric. If you're an operator who wants to build a more open, disaggregated network — and a lot of hyperscalers and tier-two cloud providers absolutely do — Nokia wants to be in that conversation at the transport layer. They're positioning for the world where U E C has enough traction to make Ethernet-based A I fabric genuinely competitive with InfiniBand on latency. Skyler: Whether the latency numbers hold up at realistic cluster scale is the question I'd be pushing on. Benchmark conditions and production conditions are very different animals, especially when you're dealing with all-reduce collective operations across thousands of endpoints. But the direction is right, and Nokia has serious transport credibility. This is worth watching as U E C moves from specification to actual silicon. Skyler: Story three takes us to Nature, which is not where I usually find my datacenter networking reads, but this is a good one. It's an industry insight piece — essentially a perspective from practitioners — on photonics as the scaling path for A I datacenters. And it covers a lot of ground, so let me pull out the parts that I think are most technically substantive. Skyler: The core argument is one that I think is increasingly hard to argue with: the electrical interconnect bottleneck is real, it's getting worse, and photonics is the long-term answer. We're at a point in A I cluster design where the bandwidth requirements between accelerators and between racks are growing faster than electrical signaling can economically deliver at distance. Copper SerDes has gotten incredibly good — PAM4 at 112 gigabits per lane, 224 coming — but physics doesn't move. Insertion loss, crosstalk, and power consumption on high-speed electrical links put a ceiling on reach and density. Skyler: The piece makes a strong case for silicon photonics specifically — not just photonics generically. Silicon photonics is interesting because it can be fabricated in CMOS-compatible processes, which means you can potentially integrate photonic components with electronics using standard foundry infrastructure. That's a very different economic model than traditional III-V photonics, which requires specialized compound semiconductor fabs. The scaling economics of silicon photonics are, in principle, CMOS-like, and CMOS-like means you can ride the manufacturing curve down in cost. Skyler: The authors also dig into the architecture question — where in the datacenter hierarchy does photonics make the most sense to deploy first? And the answer they land on is pretty consistent with industry consensus: rack-to-rack and pod-to-pod links first, then progressively closer to the chip as integration technology matures. That's the CPO trajectory we talked about in the first story, and it's also the long-range vision behind things like optical I/O directly integrated into chiplets. Skyler: One thing the piece is honest about that I really appreciate: the lasers. Silicon doesn't emit light efficiently. So you still need III-V laser sources — typically indium phosphide — either bonded to the silicon photonic chip or coupled externally. That's a manufacturing and reliability challenge that isn't fully resolved, and it affects both yield and long-term field performance. There's active research on monolithic integration of lasers, but it's not production-ready at scale. Skyler: The broader message here is that photonics isn't a niche technology for long-haul fiber anymore. It's increasingly central to how datacenters are architected at every level of the hierarchy. And the investment is following — you're seeing billions flowing into silicon photonics startups, and every major hyperscaler has serious internal photonics programs. If you're designing A I infrastructure and you're not thinking about where photonics fits in your five-year architecture, you're probably already behind. Skyler: Okay, story four, and I want to acknowledge upfront this one is a bit of a left turn from the usual territory. The headline is about protective coatings for A I datacenters — specifically, conformal coatings for circuit boards and electronics in high-density A I environments. This comes from Data Centre Dynamics, and the piece is making the argument: stop treating coatings as an afterthought. Skyler: Now, I know what you're thinking — coatings? Really? But hear me out, because there's a systems-level argument here that's actually pretty relevant to the networking and interconnect side of A I infrastructure. Skyler: Here's the deal. A I datacenters are operating at power densities that would have seemed unreasonable five years ago. We're talking GPU clusters pulling 60, 80, 100 kilowatts per rack. That heat has to go somewhere, and the thermal management solutions that work for that kind of density increasingly involve liquid cooling — direct liquid cooling, immersion cooling, two-phase cooling. And when you bring liquid closer to electronics, the risk profile for corrosion, contamination, and humidity exposure changes dramatically. Skyler: Conformal coatings — thin protective films applied to PCBs and electronic assemblies — are essentially the last line of defense for electronics reliability in these environments. The piece argues, with some data behind it, that operators who treat coatings as a commodity finishing step are setting themselves up for reliability problems at scale. The specific chemistry of the coating matters: some coatings are more resistant to specific coolants, some handle thermal cycling better, some are easier to rework when you need to repair a board. Skyler: For the interconnect and networking side specifically, think about the PCBs inside your switches, your line cards, your optical modules. Those are all subject to the same environmental stresses. A switch line card that fails because of corrosion on a connector or a trace isn't a software problem you can patch — it's a physical hardware failure that takes the link down. At the scale of an A I training cluster where network availability directly impacts compute utilization, that's a real cost. Skyler: The piece is essentially making the reliability engineering case: the decisions you make about materials and coatings during design and manufacturing have long-term operational consequences that show up in uptime numbers. It's not glamorous, but it's the kind of systems-level thinking that separates operators who hit their availability SLAs from ones who are constantly fire-fighting hardware issues. Skyler: I'll be honest, this isn't the deepest technical story we've covered today, but it's a useful reminder that A I infrastructure isn't just about the latest ASIC or the fastest optic. The physical reliability of the hardware stack matters enormously, and it's easy to underweight that when you're focused on bandwidth and latency benchmarks. Skyler: Alright, last story, and this one is a good one to close on because it's somewhat philosophical but in a productive way. EE Times is asking: is the connectivity shift inside datacenters a revolution or an evolution? And honestly, I think the answer matters for how you allocate investment and engineering attention. Skyler: The framing of the piece is around whether what we're seeing in datacenter interconnect — the push toward higher bandwidth, lower latency, CPO, new transport protocols, A I-optimized fabrics — represents a fundamental architectural break, or whether it's fundamentally the same game being played faster. And I think this is a genuinely interesting question, not just a rhetorical one. Skyler: The evolutionary case is pretty straightforward. Ethernet has been scaling for decades. Every few years you get a new speed tier — 10G to 25G to 100G to 400G to 800G, now 1.6 terabit per port on the horizon. PCIe has been the internal fabric standard for longer than most engineers remember, and it's still there at Gen 6. InfiniBand has been serving HPC and now A I for years. You could argue that what's happening now is just the next chapter in a long-running story of "more bandwidth, lower latency, at lower cost per bit." Skyler: The revolutionary case is also coherent, though. A few things are actually structurally different this time. The scale of the collective communication patterns in A I training — all-reduce across thousands of GPUs, tight synchronization requirements — is creating network requirements that didn't exist before at this scale. That's driving new transport semantics, not just faster links. U E C is an example: it's not just 800G Ethernet with better marketing, it's a genuine attempt to rethink what the transport layer does for this workload. Skyler: Second, the integration is changing. CPO isn't just faster pluggables — it's a fundamentally different relationship between the optical and electrical domains. If and when you get to optical I/O at the chiplet level, the boundary between "the chip" and "the network" starts to blur in ways that have real architectural implications. Skyler: Third, the economics are different. When you're spending hundreds of millions of dollars on a single A I training cluster, the cost of the network fabric as a fraction of total system cost is much higher than in traditional enterprise networking. That changes the investment calculus for custom silicon, custom protocols, and vertical integration in ways that don't apply to general-purpose networking. Skyler: The EE Times piece lands somewhere in the middle, which I think is right. The underlying physics and the fundamental networking principles haven't changed. But the application requirements and the economics are creating genuine pressure to innovate at every layer simultaneously — silicon, optics, protocols, software. That's not something the industry has had to do at this pace and at this scale before. Skyler: My own take: call it a revolution in the requirements, and an evolution in the response. The networking industry is good at adapting, and I think it's going to adapt here. But the window for the A I-native startups and the incumbents willing to move fast is real and finite. The architectural decisions being made right now — about CPO adoption, about which transport protocols get traction, about where intelligence lives in the fabric — are going to shape what this industry looks like for the next decade. Skyler: That's a wrap on today's Line Rate. We covered the hard realities of getting CPO to scale, Nokia's latency play in the Ultra Ethernet space, the Nature perspective on photonics as A I infrastructure's long-term foundation, a practical look at why physical reliability matters more than ever in high-density A I environments, and the revolution-versus-evolution question in datacenter connectivity. A lot of ground today — thanks for sticking with it. Line Rate, brought to you by Ada and Zen Semiconductor — Ada helps organizations integrate A I into their real workflows, and Zen Semiconductor is an umbrella company with a portfolio of businesses across the silicon industry. If you found this useful, please subscribe and share with your team — it genuinely helps the show grow. Show notes with all the source links are available wherever you're listening. See you next time.