NVIDIA CPO Switches Enter Production as AI Data Centers Embrace Silicon Photonics - remio

Skyler: Hey, welcome to Line Rate — the show tracking the chips, standards, and systems that move data at the speed of A I. I'm Skyler Monroe, and if you care about what's happening at the bleeding edge of datacenter fabric and high-speed interconnect, you're in the right place. Big thanks to our sponsors: Ada, who helps companies actually integrate A I into their real workflows, and Zen Semiconductor, an umbrella company with a portfolio of businesses across the silicon industry, including Ada on the A I deployment side. Alright, today we've got a lot to dig into — NVIDIA's co-packaged optics switches are hitting production, we're going to break down what rack-scale networking actually means, and there's some interesting movement on the open interconnect front with U E C and ESUN. Let's get into it. Skyler: So the first story is one I've been watching for a while — NVIDIA's CPO switches are entering production, and it's a big deal for where A I datacenter networking is headed. Co-packaged optics, if you're not deep in the weeds on this, is exactly what it sounds like: you take the optical components — the lasers, the modulators, the photodetectors — and you package them right alongside the switching silicon instead of putting them in separate pluggable transceivers on the front panel. And the reason you do that is fundamentally about power and bandwidth density. Skyler: When you use pluggable optics — your QSFP-DD modules, your OSFP — you're running high-speed electrical signals from the ASIC across a PCB to reach those modules. At 400 gig and 800 gig per lane, that electrical link is lossy, it burns power, and it's a real constraint on how much bandwidth you can realistically get out of a switch chip. Co-packaged optics eliminates most of that electrical trace. The photons start almost right at the die edge. You get dramatically lower power per bit and the ability to scale bandwidth in ways that pluggable just can't match at these speeds. Skyler: Now NVIDIA moving this into production is significant on a few levels. First, it validates the manufacturing maturity. CPO has been a "this is coming" technology for several years. There have been demonstrations, there have been reference designs, there have been a lot of PowerPoint slides. Actually shipping production hardware is a different statement. It means the yields are there, the thermal management is solved well enough, and the supply chain is real. Skyler: Second, it signals where NVIDIA is going with Quantum-X and beyond. If you're building a spine-leaf fabric for a massive GPU cluster — think tens of thousands of H100s or B200s — the bandwidth requirements at the switch layer are enormous. You're aggregating all that east-west traffic, all that collective communication from your all-reduce operations. CPO at the switch level is how you keep up with the GPUs themselves, which are already operating at insane memory bandwidth internally. Skyler: Third, and this is the competitive angle — this puts pressure on Broadcom, on Cisco, on Arista, on everyone in the high-radix switch space. If NVIDIA can offer a CPO-based switch that's more power-efficient and higher bandwidth density than what you can get with pluggables, that's a meaningful differentiator in a market where power budgets are absolutely the binding constraint. We're talking datacenters where the power cost is a bigger line item than the hardware itself. Skyler: One thing to keep in mind is that CPO also changes the serviceability model. With pluggable optics, if a transceiver fails, you swap it. With co-packaged, you're replacing a much more expensive and integrated unit. That's a tradeoff operators are going to have to think through carefully — but for hyperscalers building at scale, with tight operational processes, the power and performance benefits probably win that argument. Skyler: Alright, story two — The Register ran a piece on rack-scale networking, framing it as an introduction for readers who may not have been tracking how much the architecture of a rack has changed in the A I era. I want to riff on this a bit because it's a topic that sounds basic but has some real depth to it. Skyler: The traditional model of rack networking is pretty simple: you've got servers in a rack, a top-of-rack switch handles the Ethernet uplinks, and you connect those ToR switches up to your aggregation and spine layers. Works great for general-purpose compute. For A I training workloads, it's increasingly the wrong mental model. Skyler: What's changed is that the communication pattern inside a training job is massively different from a typical web-service or database workload. In a big transformer training run, you have allreduce collectives happening continuously across potentially thousands of GPUs. Every GPU needs to exchange gradient information with every other GPU in its collective group, and the latency and bandwidth of those exchanges directly determine how efficiently your training scales. This is not your grandfather's north-south datacenter traffic. Skyler: So rack-scale networking, the way it's being discussed now, treats the rack — or a group of racks — as a first-class networking domain. You're thinking about the interconnect fabric within and between racks as a coherent system, not just a collection of Ethernet switches. Technologies like NVLink Switch from NVIDIA, or the various A I fabric approaches from startups like Enfabrica and Axelera, are all trying to optimize specifically for this collective-heavy, all-to-all communication pattern. Skyler: The interesting architectural question is where you draw the boundary. NVLink gives you extremely high bandwidth within a node or a small cluster of nodes — we're talking terabits per second of bisection bandwidth — but it's proprietary and doesn't extend far. Ethernet-based fabrics like those built on U E C or just standard RDMA over Converged Ethernet scale further but with different latency and bandwidth tradeoffs. The emerging answer is that you probably use multiple network tiers: a tight, high-bandwidth in-rack or in-pod fabric, and then a scale-out Ethernet fabric for inter-pod communication. Skyler: What rack-scale networking really means in practice is that the networking team and the compute team can no longer operate in separate silos. The topology of the fabric — the number of hops, the bisection bandwidth, the routing algorithm — directly affects the throughput of the A I workload. That's a cultural shift as much as a technical one, and honestly, it's one of the bigger organizational challenges I see at hyperscalers and at the big cloud providers trying to build competitive A I infrastructure. Skyler: The Register's piece is a good entry point for people coming to this fresh, and I'd encourage anyone who's newer to the A I fabric space to read it. But for this audience, I think the real takeaway is that "rack-scale" is shorthand for a much deeper architectural rethink — from how you cable the physical layer all the way up to how your collective communication library sees the topology. Skyler: Okay, story three is also about co-packaged optics but from a different angle — Network World did a solid explainer on what CPO is and why it's becoming the solution for the capacity crunch in A I datacenter networks. I want to use this as a chance to go a bit deeper on the physics of why pluggable optics hit a wall. Skyler: The fundamental issue is the electrical-optical interface. In a traditional pluggable module, your switch ASIC sends a high-speed SerDes signal down a trace on the PCB to a connector, and then into the module where it gets converted to light. At 56 gigabaud and above — which is where 400 gig and 800 gig per-lane signaling lives — that electrical signal is attenuated, it picks up noise, and it requires significant DSP and equalization to recover cleanly on the other side. All of that DSP burns power. The module itself is pulling watts just to clean up the signal it received from the ASIC. Skyler: With co-packaged optics, you dramatically shorten that electrical path. The optical engine — whether it's a silicon photonics die or a discrete set of photonic components — sits right next to the switch ASIC in the same package. The electrical channel between the ASIC and the photonics might be measured in millimeters rather than centimeters. You lose less signal, you need less equalization, and you save a lot of power. Numbers being thrown around in the industry are in the range of 30 to 50 percent lower power consumption for the optical interconnect versus comparable pluggable solutions. Skyler: Now there's a few different architectural approaches to CPO worth knowing. You've got near-package optics, which puts the optical engine on the board very close to the ASIC but not in the same package — that's a stepping stone, lower integration, easier to manufacture. Then you've got on-package approaches where the photonics and the switch silicon are co-packaged using chiplet-style integration — 2.5D interposers, silicon bridges, that kind of thing. And then there are proposals for even tighter integration, putting photonic structures directly on the same die as the logic, though that's harder given the process technology differences between photonics and logic. Skyler: The supply chain piece is something the Network World article touches on that I think is underappreciated. Co-packaged optics requires tight collaboration between the switch ASIC vendor, the photonics vendor, and the package substrate supplier. NVIDIA has the advantage of being vertically integrated enough to drive that coordination internally. For merchant silicon vendors, that means closer partnerships with companies like Coherent, II-VI, or silicon photonics players like Intel's photonics group, or Marvell's optical DSP business. It's not a one-company problem. Skyler: The article also frames CPO as the solution for surging capacity, and I think that framing is right but with a caveat — CPO solves the power-per-bit problem, but it doesn't by itself solve the fiber infrastructure challenge. You still need the fiber plant, the amplification for longer reaches, the coherent DSP for DCI links. CPO is transformative for the switch-to-switch and switch-to-server intra-datacenter links, but it's one piece of a broader capacity story. Keep that in context when you're hearing the hype. Skyler: Story four — and this one is close to my heart because it's about the open interconnect standards battle. SDxCentral reported that a Broadcom engineer publicly backed ESUN and U E C as the key open interconnect pivot points for A I fabrics going forward. Let's unpack what that means. Skyler: U E C is the Ultra Ethernet Consortium spec. It's an effort — backed by AMD, Cisco, Hewlett Packard Enterprise, Intel, Meta, Microsoft, and others — to make standard Ethernet work better for A I workloads. The core problem U E C is solving is that traditional TCP-based Ethernet is not great for collective communications. The congestion control is too slow, the latency tail is too high, and the in-order delivery requirements don't match well with how you want to move gradient tensors around. U E C is adding things like new transport semantics, better multipath support, and packet-level optimizations to address this. Skyler: ESUN — and this is one that's a bit less in the spotlight — stands for Ethernet Special Use Network, and it's a related but distinct effort focusing on the specific signaling and media access layer enhancements needed for these high-radix A I fabrics. The Broadcom engineer's comments are essentially saying: look, if you want a vendor-neutral, open path to scaling A I networking, U E C and ESUN together give you that path. You're not locked into NVLink, you're not locked into any proprietary collective fabric. Skyler: And this is where it gets politically interesting. Broadcom is the dominant merchant switch silicon vendor — Tomahawk and Jericho series are in a huge fraction of deployed datacenter switches globally. When a senior Broadcom engineer publicly endorses open standards over proprietary approaches, it's not a neutral technical opinion. It's a business signal. Broadcom's business model depends on selling switch chips to everyone, and everyone includes hyperscalers who would rather not be locked into NVIDIA's NVLink ecosystem. So Broadcom has a structural incentive to champion open Ethernet-based alternatives. Skyler: That said, the technical case for U E C and ESUN is real and stands on its own. The challenge is timing and spec maturity. U E C has been in development for a couple of years now and the full spec — particularly the transport layer — is still evolving. Implementations exist, interop testing is happening, but it's not a done deal yet. If you're a hyperscaler making fabric decisions for a datacenter that won't be fully operational for 18 months, you're making a bet on where U E C lands, not where it is today. Skyler: U A Link is also in this conversation, though it's addressing a different layer — it's about the scale-up interconnect within a multi-GPU node, comparable to NVLink's domain, whereas U E C is more about the scale-out network between nodes. The fact that you have open alternatives emerging at both layers — U A Link for scale-up, U E C for scale-out — is a genuinely important development for anyone who wants A I infrastructure that isn't entirely controlled by a single vendor. Skyler: My read is that the endorsement from a Broadcom engineer matters because Broadcom has the silicon execution to actually back these standards with real chips. If the next generation of Tomahawk is natively U E C-capable, that accelerates adoption significantly. Watch for silicon announcements that go beyond just consortium membership. Skyler: Last story — Technetbook covered the GTC 2026 angle on silicon photonics, specifically around the Rubin Ultra chip launch and what that means for CPO and datacenter infrastructure trends going into next year. I want to zoom out a bit here and talk about where we are in the arc of this technology. Skyler: Rubin is NVIDIA's next-generation GPU architecture coming after Blackwell. Rubin Ultra is the high-end variant — dense, power-hungry, and going to need a lot of bandwidth to keep those GPUs fed with data. The connection to silicon photonics and CPO is direct: as GPU compute density increases, the memory bandwidth and interconnect bandwidth requirements grow proportionally. You can't just keep throwing more pluggable transceivers at the problem because you run out of front-panel space and power headroom. Skyler: What NVIDIA is signaling with the Rubin-era roadmap is that CPO isn't a nice-to-have anymore — it's a required part of the infrastructure stack. And they're not alone in this trajectory. Intel's roadmap, Broadcom's roadmap, Marvell's roadmap — they all point in the same direction. Silicon photonics is becoming a foundational technology for the datacenter, not a specialty item. Skyler: The silicon photonics piece specifically is interesting because it enables integration at scale. Traditional III-V semiconductor photonics — things like indium phosphide lasers — are extremely high performance but difficult to integrate tightly with CMOS logic. Silicon photonics uses standard CMOS-adjacent processes, which means you can leverage existing semiconductor manufacturing infrastructure. Companies like Intel, Cisco, and a bunch of startups have been building silicon photonics capabilities for a decade. That groundwork is now paying off as CPO demands scale. Skyler: One nuance from the GTC 2026 coverage is the question of where the laser source lives. Silicon is not a great light emitter — it's indirect bandgap — so even silicon photonics chips need an external laser source, typically indium phosphide or other III-V material, that gets edge-coupled or butt-coupled into the silicon photonic waveguides. Managing those laser sources, their thermal sensitivity, their reliability over the life of a switch, is an ongoing engineering challenge. There's interesting work happening on hybrid bonding approaches that put III-V gain material directly onto silicon photonic chips, which could help, but it's not universally solved. Skyler: The market implication here is that the component supply chain for silicon photonics is becoming strategically critical infrastructure. We're already seeing NVIDIA and the hyperscalers making investments and long-term agreements with photonics component suppliers. The companies that can reliably supply high-quality photonic integrated circuits at scale — coherent transceivers, silicon photonics foundries, laser sources — are in an increasingly powerful position. Skyler: And zooming out to the GTC 2026 context: NVIDIA using a major launch event to put silicon photonics and CPO front and center is a messaging choice. It's telling the market that the GPU is not just a compute product anymore — the full system, including how it connects to the network, is part of the value proposition. That has implications for every company in the optical supply chain, and it has implications for how datacenter architects think about the total cost and total power budget of a Rubin-era cluster. The optics are not an afterthought. They're part of the chip story now. Skyler: Alright, that's a wrap on today's Line Rate. We covered a lot of ground — NVIDIA's CPO switches going to production, the evolving meaning of rack-scale networking, the physics and supply chain of co-packaged optics, Broadcom's endorsement of U E C and ESUN as the open interconnect path forward, and what Rubin Ultra and GTC 2026 signal about silicon photonics becoming table stakes infrastructure. Massive thanks to our sponsors — Line Rate, brought to you by Ada and Zen Semiconductor. Ada helps companies actually integrate A I into their workflows in a practical way, so check them out. And Zen Semiconductor is an umbrella