OFC 2026 Summary: How Silicon Photonics, CPO, OCI, and OCS Are Redefining the Physical Boundaries of Data Centers - semivision

Skyler: Welcome to Line Rate — the show tracking the chips, standards, and companies defining how A I data centers move data. I'm Skyler Monroe, and if it's happening at the physical layer of A I fabric, we're covering it here. Big thanks to our sponsors Ada, who helps organizations actually integrate A I into their real workflows, and Zen Semiconductor, an umbrella company with a portfolio of businesses across the silicon industry. Today we've got a packed show — OFC 2026 takeaways, co-packaged optics making its move as the backbone of A I interconnect, Meta pulling back the curtain on how they run RoCE at massive scale, the first U E C and U A Link IP hitting the market, and Corning's CEO putting a ten-billion-dollar number on the data center opportunity. Let's get into it. Skyler: So OFC 2026 just wrapped, and if you follow optical interconnect at all, the vibe coming out of this year's show was pretty clear — silicon photonics, co-packaged optics, optical circuit switching, and optical compute interconnect are no longer just research talking points. They are rapidly becoming the architectural vocabulary of the next generation of data centers. Let me break down what each of those threads actually means and why they matter. Skyler: Silicon photonics first. The core pitch here is that you can fabricate optical components — modulators, photodetectors, waveguides — using standard CMOS processes. That means you get the cost curves and integration density of semiconductor manufacturing applied to optical components. What OFC 2026 showed is that the industry has gotten genuinely good at this. The yields are up, the insertion loss numbers are tighter, and critically, the integration story with electrical ASICs is maturing. You're not just building discrete optical components anymore — you're building photonic integrated circuits that can sit right next to, or in some cases on the same package as, the switching silicon. Skyler: Co-packaged optics — CPO — is the natural evolution of that. Instead of running electrical signals out of a switch ASIC to a pluggable transceiver in a faceplate cage, you put the optical engine directly on the package with the ASIC. The electrical distance from the SerDes to the optical modulator goes from centimeters to millimeters. And that matters enormously because power consumption in high-speed electrical interconnect scales with distance and data rate in a pretty brutal way. At 51.2 terabits per second switch capacity and beyond, the power budget for getting signals off the chip is genuinely a limiting factor. CPO attacks that directly. Skyler: The OFC conversation this year also had a lot of energy around OCI — optical compute interconnect — which is about extending those same ideas from the switching layer into the compute layer itself. Connecting GPUs and accelerators with optical links rather than copper or even traditional pluggable fiber. And then OCS — optical circuit switching — which is a different angle, using fast all-optical switches to reconfigure the physical topology of the network dynamically. That's interesting for A I training workloads in particular, where your traffic patterns are highly structured and somewhat predictable across the collective communication phases. If you can match your physical topology to your logical collective pattern, you can cut a lot of unnecessary hops. Skyler: The big picture from OFC 2026 is that the physical boundaries of what we think of as a data center are getting blurry. CPO and OCI push optics into the compute package. OCS pushes reconfigurability into the physical layer. And high-bandwidth silicon photonics modules are extending the reach of what you can call a coherent cluster. The definition of where one data center ends and another begins is genuinely shifting. For architects and silicon teams, the message is: the electrical-optical boundary is moving fast, and where you draw that line in your system design is one of the most consequential decisions you're making right now. Skyler: Okay, let's stay on co-packaged optics for a moment but zoom in on the A I data center angle specifically, because there was a good piece out of Pandaily framing CPO as the interconnect backbone for A I data centers, and I think it's worth unpacking why that framing is gaining traction. Skyler: The A I training workload has some very specific interconnect characteristics that make traditional pluggable transceiver architectures increasingly uncomfortable. You've got enormous all-reduce traffic, high bandwidth sensitivity, and latency that directly affects how efficiently you can overlap compute and communication in your training pipeline. The classic approach — switch ASIC with pluggable QSFP or OSFP transceivers — works, but at 800 gigabit and moving toward 1.6 terabit per lane speeds, you're fighting physics on the electrical trace from the ASIC to the faceplate, and you're burning a lot of power in retimers and the transceiver optics themselves. Skyler: CPO changes that calculus. With the optical engine co-located on the package, you cut the electrical path length dramatically, which means lower insertion loss, lower power per bit, and better signal integrity without heroic retimer engineering. The numbers being cited at OFC were around thirty to forty percent power reduction for the optical I/O portion of a switch compared to pluggable alternatives at equivalent data rates. At the scale of a hyperscaler spine or an A I training cluster, that is not a rounding error — that is hundreds of kilowatts per deployment. Skyler: The knock on CPO historically has been repairability and replaceability. With a pluggable transceiver, if a port fails, you swap the transceiver. If your optical engine is on the package, a failure potentially means replacing the whole switch. That's a real operational concern, and the industry has been wrestling with it. The emerging answer involves two tracks — one is making the optical engine modular enough that it can be replaced without replacing the ASIC package, and the other is investing in reliability to the point where the failure rate argument becomes less compelling. Neither track is fully solved, but both are making progress. Skyler: The competitive landscape here is fascinating. You've got merchant silicon vendors, optical module makers, systems integrators, and hyperscalers all having opinions about where the optical engine should live and who should build it. The hyperscalers in particular have strong incentives to push CPO adoption because the power and cost savings accrue to them directly. And when hyperscalers push hard on a technology transition, it tends to happen faster than the rest of the industry expects. For anyone building networking silicon or optical components right now, understanding your position in the CPO ecosystem is not optional. Skyler: Alright, let's shift from optical interconnect to the software and protocol layer, because Meta dropped a really substantial engineering blog post this week on how they run RoCE — Remote Direct Memory Access over Converged Ethernet — for distributed A I training at scale, and it's one of the more candid looks at production A I fabric we've gotten from a hyperscaler. Skyler: For context, RoCE is an RDMA transport protocol that runs over standard Ethernet, and it's become one of the dominant choices for A I training cluster fabric alongside InfiniBand. The pitch for RoCE over InfiniBand is basically: you get RDMA semantics and low latency without the proprietary network stack, and you can leverage the existing Ethernet ecosystem in terms of silicon, tooling, and operational expertise. The tradeoff is that Ethernet was not originally designed for the lossless, low-latency, high-throughput behavior that RDMA really wants, so you end up doing a fair amount of engineering to get there. Skyler: What Meta's post gets into is how that engineering actually looks at their scale. They're running RoCE across networks with tens of thousands of GPUs, and the challenges they're dealing with are genuinely hard. Congestion control is a big one — when you have thousands of flows all hammering the same all-reduce collective, you get incast congestion at the receiving side that can absolutely destroy throughput if you're not careful. Meta's approach involves a combination of DCQCN — Data Center Quantized Congestion Notification — tuning, careful traffic shaping, and what they describe as flow-level load balancing that goes beyond simple ECMP hashing. Skyler: They also get into fabric topology choices and how they've structured the network to minimize the blast radius of congestion events. The key insight is that A I training traffic is fundamentally different from general-purpose data center traffic — it's highly synchronized, it comes in big bursts aligned to gradient synchronization points, and a single slow link or congested port can hold up thousands of GPUs waiting for an all-reduce to complete. That synchronization means traditional congestion control algorithms that were tuned for more bursty, asynchronous traffic can actually make things worse in certain configurations. Skyler: One thing that's particularly interesting in Meta's writeup is how much of the operational complexity lives in the interaction between the transport protocol, the collective communication library, and the actual training framework. This isn't just a networking problem — it's a co-design problem across the full stack. And Meta has the scale and the internal tooling to do that co-design in a way that a lot of enterprises and smaller A I shops simply can't. The fact that they're publishing this is genuinely valuable for the community, because it gives everyone a more grounded picture of what production scale RoCE actually requires. Skyler: The broader context here is the ongoing comparison between RoCE and InfiniBand. InfiniBand, particularly with NVIDIA's acquisition of Mellanox, has a very tight integration story with GPU collectives — the SHARP in-network compute features, the HDR and NDR speed roadmap, the NCCL optimizations. RoCE's advantage is openness and ecosystem breadth. Meta's writeup is essentially a case study in how far you can push RoCE if you're willing to invest in the engineering. And at their scale, the economics of avoiding proprietary lock-in are enormous, which is why they're willing to invest that engineering effort. Skyler: Now let's talk about something that's been on the standards roadmap for a while and is finally getting real — the first intellectual property blocks supporting both U E C and U A Link have been announced, which is a pretty significant milestone for both of these emerging interconnect standards. Skyler: Quick level-set on the two standards for anyone who needs it. U E C — Ultra Ethernet Consortium — is building a next-generation Ethernet transport designed specifically for A I and HPC workloads. The goal is to keep the openness and ecosystem advantages of Ethernet while adding the transport features that A I training needs — things like out-of-order packet delivery, multipath, RDMA-friendly congestion control, and tight integration with collective communication semantics. The consortium has grown substantially and includes most of the major names in networking silicon, systems, and hyperscalers. Skyler: U A Link — Unified Accelerator Link — is a different layer of the problem. Where U E C is about the network fabric connecting machines, U A Link is about the high-bandwidth, low-latency interconnect between accelerators within a system or a very tightly coupled scale-up domain. Think of it as the open alternative to NVLink — NVIDIA's proprietary GPU-to-GPU interconnect. The pitch is that with U A Link, you could build scale-up domains using accelerators from different vendors interconnected over an open standard, rather than being locked into a single vendor's proprietary fabric. Skyler: The announcement of actual synthesizable IP blocks supporting both standards is significant for a couple of reasons. First, it means the standards are mature enough that someone is willing to put engineering resources into building commercial silicon implementations. IP blocks are how standards actually get into ASICs — you license the verified RTL, you integrate it into your design, and you get the protocol behavior without having to build it from scratch. When IP becomes available, the time from "standard exists" to "silicon ships" compresses dramatically. Skyler: Second, having a single IP vendor supporting both U E C and U A Link suggests someone sees a world where both standards are in the same system — scale-up fabric within a pod handled by U A Link, scale-out fabric between pods handled by U E C. That's actually the architecture a lot of people think makes sense for large A I training clusters. You want the ultra-low latency, high bandwidth, all-reduce-optimized behavior for your tightly coupled scale-up domain, and you want the openness and reach of Ethernet-based fabric for scale-out. Skyler: I want to be careful about timelines here, because both U E C and U A Link are still evolving specifications. The IP availability is a real milestone, but we're not at the point where silicon is shipping in production systems. The U E C specification is still being finalized in some important areas, and U A Link is even earlier in that process. What this announcement tells us is that the ecosystem is building confidence that these standards will ship, which creates a bit of a self-fulfilling dynamic — IP availability accelerates silicon development, which accelerates deployment, which validates the standard. Watch this space through the end of 2025 and into 2026. Skyler: Last story today, and honestly it might be the one that crystallizes the whole episode — Corning's CEO went on record saying that the data center scale-up and scale-out opportunity represents a ten-billion-dollar revenue stream for Corning. Let's sit with that number for a second. Skyler: Corning is a fiber and glass company. They make optical fiber, fiber cables, and related connectivity products. They are not a semiconductor company. They are not building A I chips. They are not in the switch ASIC business. And their CEO is saying that the physical data center interconnect market — the fiber and optical hardware that connects everything together — is a ten-billion-dollar revenue opportunity for them specifically. That tells you something pretty profound about the scale of what's being built. Skyler: The framing Corning is using — scale-up versus scale-out — maps pretty well to the U E C and U A Link conversation we just had. Scale-up is about the high-bandwidth connections within a compute pod, within a rack, within a tightly coupled accelerator cluster. Scale-out is about connecting pods to each other, connecting clusters to storage, connecting data centers over longer distances. Both require enormous amounts of fiber, and both are growing at rates that traditional enterprise networking markets simply cannot match. Skyler: What's driving the scale-up fiber demand specifically is the architecture of modern A I clusters. A single NVLink domain for current-generation NVIDIA systems, or the equivalent scale-up domains being built with custom accelerators at hyperscalers, requires huge amounts of high-bandwidth, short-reach optical connections. When you're building at the scale of thousands of GPUs in a tightly coupled pod, the fiber count is staggering — and that's before you even think about the scale-out spine connecting those pods. Skyler: The scale-out story is maybe even more interesting in terms of the growth curve. Every hyperscaler is building multiple large A I training clusters, and those clusters need to communicate with each other, with storage systems, and with inference endpoints. The bandwidth requirements for that fabric are growing faster than general internet traffic, faster than enterprise WAN traffic, faster than basically any other segment of the networking market. And all of that traffic rides fiber. Skyler: Corning putting a ten-billion-dollar number on this publicly is significant because Corning is not a company that tends to make splashy forward-looking claims. They are a very operationally grounded business. When their CEO says ten billion dollars, they've done the demand planning with their hyperscaler customers. They've seen the purchase orders coming. This is a bottoms-up number, not a top-down analyst projection. And it's a useful sanity check on all the hand-waving about A I infrastructure spending — when the fiber supplier is calling a ten-billion-dollar opportunity, the infrastructure buildout is real and it is enormous. Skyler: The other thing I'd note is that this creates interesting dynamics upstream in the supply chain. Silicon photonics components need optical fiber. CPO deployments need fiber patchbays and cable assemblies. OCS systems need high-density fiber routing. The more the industry moves toward optical interconnect at every layer of the architecture, the more the fiber and optical component supply chain becomes a strategic bottleneck. Corning's positioning here is not accidental — they're making sure everyone knows they are ready to be that supply chain. Skyler: Alright, that's a wrap on today's show. We went from the physical layer — silicon photonics and co-packaged optics at OFC — through the protocol layer with Meta's RoCE deep dive, up to the emerging standards layer with U E C and U A Link IP, and then pulled back to the big infrastructure picture with Corning's ten-billion-dollar data center call. The through-line in all of it is the same: the data center fabric for A I is being rebuilt from the ground up, faster than most people expected, and the decisions being made in silicon and standards right now are going to define how that infrastructure looks for the next decade. Thanks for listening to Line Rate, brought to you by Ada — who helps organizations integrate A I into their real-world workflows — and Zen Semiconductor. If you found this useful, please subscribe and share it with a colleague who's deep in this space. Show notes with links to everything we covered are on the website. I'll see you next week.