AI data center optical interconnect market to hit $144 billion by 2030, an over ten-fold increase from 2024 figures, according to new projections — silicon photonics expected to account for nearly two-thirds of revenue, driven by co-packaged optics - Tom's Hardware

Skyler: Welcome to Line Rate — the show that tracks every chip, cable, standard, and consortium announcement shaping the datacenter fabric and A I interconnect space. I'm Skyler Monroe, and if it moves bits between GPUs, across racks, or datacenter to datacenter, we're talking about it here. Big thanks to our sponsors today — Ada, which helps organizations actually integrate A I into their real workflows, and Zen Semiconductor, an umbrella company with a portfolio of businesses across the silicon industry, including Ada. Really appreciate their support. Alright, we've got a packed episode — a 144 billion dollar optical market projection, Marvell's scale-up network pitch, a co-packaged optics benchmarking report that names names, Broadcom's Thor Ultra dropping into the A I networking conversation, and a really interesting piece about how A I workloads are collapsing the line between network, memory, and storage. Let's get into it. Skyler: So let's start with the big number that's been making the rounds this week. According to new market projections reported by Tom's Hardware, the A I datacenter optical interconnect market is expected to hit 144 billion dollars by 2030. That's a more than ten-fold increase from where we are in 2024. And if you're in this space, that number probably doesn't shock you — but it's worth unpacking why the trajectory looks like that, because it's not just "A I is growing, therefore optics." Skyler: The real story is silicon photonics and co-packaged optics, which the projections say will account for nearly two-thirds of that 144 billion dollar figure. That's a massive structural shift from where the optical interconnect market has lived for most of its history — which is pluggable modules hanging off the front panel of a switch or a line card, doing the electro-optical conversion out at the edge of the system. Skyler: Co-packaged optics flips that model. Instead of running the electrical signal from the switching ASIC all the way out to a pluggable at the faceplate — which means you're eating signal loss and power the whole way — you bring the optical engine right up next to the chip. We're talking millimeters of electrical trace instead of centimeters. That matters enormously at the signaling rates we're talking about now. 800 gig per lane, 1.6 terabit interfaces — the physics of long electrical traces become genuinely painful at those speeds. Skyler: And silicon photonics is the manufacturing technology that makes this viable at scale. It lets you build the optical components — modulators, detectors, waveguides — using standard CMOS-compatible fab processes. You're not hand-assembling exotic III-V components. You're running wafers. That's the cost and scalability unlock that changes the economics of co-packaged optics from "interesting research project" to "supply chain-ready product." Skyler: Now, 144 billion by 2030 is a big number with a lot of assumptions baked in. A I build-out has to stay aggressive, the hyperscalers have to actually commit to co-packaged optics at volume — which they are, but the transition takes time — and the supply chain for silicon photonics has to mature fast enough to meet demand. None of those are guaranteed. But directionally, the forces are real. Every generation of GPU cluster is more bandwidth-hungry than the last, and the only way to feed that without burning your power budget on SerDes and re-timers is to get the optics closer to the silicon. That's not a market forecast, that's physics. Skyler: Alright, story two. Marvell put out a piece this week on what they're calling their scale-up network solutions for A I infrastructure. Now, for listeners who aren't living in the Marvell universe, a bit of context: Marvell is one of the key players in custom silicon and optical DSPs, and they've been positioning hard around A I networking — both the scale-up side, which is the interconnect inside a training cluster, GPU to GPU, and the scale-out side, which is the spine of the broader datacenter network. Skyler: Scale-up is the harder problem in a lot of ways. When you're doing inference or training on a large model, the GPUs need to talk to each other constantly — gradient synchronization, all-reduce operations, activation transfers. The latency and bandwidth on those links is directly on the critical path of your training job. This is why NVLink exists, and it's why everyone is fighting so hard over what the alternative looks like for non-NVIDIA clusters. Skyler: Marvell's angle here is that they have pieces across the stack — they make Ethernet PHYs, optical DSPs, and they're doing custom ASIC work for hyperscalers. Their scale-up pitch is built around the idea that you can build a competitive fabric using high-speed Ethernet-based interconnects with the right DSP technology to handle the signal integrity at these distances and speeds. Skyler: What's interesting is where Marvell sits relative to the standards landscape. UEC — the Ultra Ethernet Consortium — is trying to define an open, Ethernet-based answer to the scale-up problem. And Marvell is a member. But in practice, most hyperscalers are not waiting for UEC to finalize specs before they start building. They're making decisions now based on what's available, what's proven, and what their custom silicon can support. So Marvell is navigating a world where they need to have standards-aligned solutions and proprietary custom silicon solutions at the same time. Skyler: The co-packaged optics piece matters a lot here too. If your scale-up fabric is going to run at the speeds A I training clusters need — we're talking about hundreds of terabits of bisectional bandwidth in a large pod — the interconnect technology has to scale. Marvell's DSP portfolio is positioned as the bridge between the switching ASICs and the optical medium in a CPO world. That's a real differentiator if they can execute, and it's a battleground that Broadcom, Cisco, and a bunch of startups are all competing on. Skyler: Story three is a market research report from ResearchAndMarkets.com, picked up by Business Wire, covering the co-packaged optics market from 2026 to 2036. Now I'll be honest — market research reports are a mixed bag. Sometimes they're genuinely useful for understanding the competitive landscape. Sometimes they're mostly recycled press releases with a price tag. But this one is interesting because it specifically names products: Nvidia's Spectrum-X, Nvidia's Quantum-X, and something called the Bailly platform — and it promises start-up innovation mapping and foundry comparisons. Skyler: Let's talk about what those platforms actually are, because the names matter. Spectrum-X is Nvidia's Ethernet-based networking platform — it's their answer for A I scale-out, built on top of their Spectrum-4 switching silicon and combined with BlueField DPUs. It's designed for A I workloads over Ethernet, which is a big deal because Ethernet is where most of the non-NVIDIA-proprietary ecosystem lives. Skyler: Quantum-X is Nvidia's InfiniBand platform — that's the higher-performance, lower-latency fabric that's been the backbone of serious HPC and A I training clusters for years. InfiniBand has latency and collective operation advantages over traditional Ethernet, though UEC is explicitly trying to close that gap. Skyler: The Bailly platform is interesting — that's associated with Intel's Gaudi accelerator ecosystem, which is Intel's attempt to build a competitive A I training platform. Intel has had a rough road with Gaudi in terms of adoption, but they're still in the game and the interconnect story matters. Skyler: The co-packaged optics angle across all three is what the report is digging into — which foundries are manufacturing the optical engines, how the different platforms compare on CPO integration, and where the startups are finding gaps to fill. The foundry comparison piece is important because this is where TSMC, Intel Foundry, GlobalFoundries, and a few others are competing for the silicon photonics volume that's coming. Getting designed into the right platform early is going to define the next decade for a lot of those foundry relationships. Skyler: The start-up innovation mapping is where I'd look most closely. The incumbents are named, but the disruption in co-packaged optics is probably going to come from companies that aren't Nvidia or Intel — optical chiplet startups, novel modulator approaches, heterogeneous integration specialists. That's where the next generation of the supply chain is being built right now. Skyler: Alright, story four. Broadcom drops what Network World is calling "Thor Ultra" for A I networking. Let me give you the Broadcom context first. Broadcom is arguably the most important switching ASIC company in the world for datacenter networking. Their Tomahawk and Jericho lines are in basically every major datacenter. And in the A I networking space, they've been pushing their Tomahawk 5 and their Ultra Ethernet-aligned roadmap. Thor is a different beast — that's Broadcom's A I networking ASIC aimed directly at the scale-up problem. Skyler: Thor Ultra is the next step in that line, and the "Ultra" naming implies a substantial jump. If we're following Broadcom's roadmap logic, we're likely talking about higher radix, higher bandwidth per port, and better support for the collective operation patterns that A I training workloads actually generate. Collectives — all-reduce, all-gather, reduce-scatter — are not traditional network traffic. They're bulk synchronization operations where every endpoint is talking to every other endpoint simultaneously, and the fabric has to handle that without killing your training throughput. Skyler: Broadcom's pitch for Thor has always been that you can build a high-performance A I fabric on Ethernet — open, competitive, not locked to NVLink — if you have the right switching silicon and the right protocol enhancements. UEC is the standards umbrella for those enhancements, and Broadcom has been one of the most aggressive voices in the UEC ecosystem. Though it's worth saying — UEC specs are still evolving. The consortium has published profiles, but full interoperability between vendors is still a work in progress, and hyperscalers are doing a lot of custom tuning on top. Skyler: Thor Ultra competing directly with Nvidia's Quantum-X InfiniBand and their own Spectrum-X on the Ethernet side is the real competitive dynamic here. Broadcom is betting that the open ecosystem play wins — that hyperscalers and tier-two cloud providers would rather buy switching silicon from Broadcom and build their own fabric than pay the NVLink premium. And for a lot of customers, especially the ones doing large inference deployments rather than frontier training, that calculation might well be right. Skyler: The co-packaged optics tie-in here matters too. Thor Ultra, running at the bandwidth levels they're targeting, is going to need CPO to make the power and signal integrity math work. So watch for announcements about which optical engine partners Broadcom is aligning with. That ecosystem decision will shape what the Thor Ultra supply chain looks like. Skyler: Last story, and this one is a bit more conceptual, but it's one of my favorites because it's about a shift that's happening under the surface of all the other stories we talk about. Semiconductor Engineering ran a piece this week with the thesis that A I workloads are turning the datacenter network into a combined memory and storage fabric. And if you think about what that actually means architecturally, it's a pretty profound statement. Skyler: Traditional datacenter networking was designed around a pretty clean separation of concerns. You had your compute nodes, your storage arrays, your memory — and the network was the thing that connected them, moving messages and data between clearly defined endpoints. Each tier had its own interface standard, its own optimization target, its own latency budget. Skyler: A I training breaks all of that. When you're doing a forward and backward pass on a multi-hundred-billion parameter model, the distinction between "memory" and "network" starts to dissolve. Model weights that don't fit in HBM have to live somewhere, and they have to move to where the compute is — fast. KV cache for large context windows has to be accessible across the cluster. Gradient accumulation happens across nodes in ways that look a lot more like distributed memory access than traditional message passing. Skyler: The industry response to this is what's making the networking stack so interesting right now. You've got CXL — Compute Express Link — trying to extend cache-coherent memory semantics across PCIe and eventually across the network. You've got NVLink-C2C doing something similar in Nvidia's ecosystem. You've got RDMA over Ethernet, which has been around for years but is being pushed hard in A I clusters. And you've got new proposals around disaggregated memory pools that sit on the fabric and get accessed by multiple compute nodes simultaneously. Skyler: The practical implication for fabric architects is that you can't design the network for traditional latency and throughput metrics anymore and call it done. You have to understand the A I workload access patterns — which tensors are hot, how the collective operations map to the topology, where the KV cache needs to live relative to the inference engines. That's a fundamentally different design conversation than "how do I route packets efficiently." Skyler: And for the standards folks — this is why you're seeing so much activity at the intersection of CXL, PCIe, and Ethernet right now. UEC is trying to capture some of the memory-semantic use cases within an Ethernet framing. CXL 3.0 and beyond is pushing toward fabric-attached memory that multiple hosts can access. The boundaries are dissolving, and the companies that figure out how to build silicon that spans those boundaries — whether that's a smart NIC, a CXL switch, a memory controller with fabric connectivity — those are the ones that are going to be incredibly well positioned for the next generation of A I infrastructure. Skyler: It's messy and it's fast-moving, which is exactly why we're here talking about it every week. Skyler: Alright, that's a wrap on this episode of Line Rate. Big week — 144 billion dollar optical market, Marvell scaling up, CPO benchmarks naming names, Broadcom's Thor Ultra in the A I fabric fight, and the blurring line between network, memory, and storage. Thanks again to our sponsors — Ada, which helps businesses actually integrate A I into their workflows in meaningful ways, and Zen Semiconductor, an umbrella company with a portfolio across the silicon industry. If you got value out of today's episode, please subscribe and share it with someone in your orbit who cares about where the datacenter is headed. Show notes with links to everything we covered are in the usual place. I'm Skyler, this is Line Rate, brought to you by Ada and Zen Semiconductor — see you next time.