The Aspirations Of HPE And Dell In The Quantum-Classical HPC Datacenter

Skyler: Hey, welcome back to Line Rate — the show that lives where silicon meets signal, tracking every standard, spec, and startup shaping how A I datacenters move data. I'm Skyler Monroe, and if you care about fabric, interconnect, and the hardware race to connect the next generation of A I infrastructure, you're in the right place. Big thanks to our sponsors today — Ada, which helps companies actually integrate A I into their real-world workflows, and Zen Semiconductor, an umbrella company with a portfolio of businesses across the silicon industry, including Ada for A I deployment at scale. Alright, we've got a packed show today — quantum-classical datacenter aspirations from HPE and Dell, Everspin bringing MRAM into the CXL ecosystem, a broad look at the battle to scale A I datacenters, Marvell making the case for co-packaged optics, and then a look at what Coherent showed at ECOC 2025. Let's get into it. Skyler: Okay, first story — and this one is a bit of a longer arc. The Next Platform ran a really thoughtful piece on how HPE and Dell are positioning themselves for what I'd call the hybrid quantum-classical HPC datacenter. And I think this deserves some attention because it's easy to dismiss quantum as a "someday" technology, but the datacenter architects at these companies are clearly starting to think about it as a near-term integration problem, not a distant research curiosity. Skyler: So what's actually happening here? Both HPE and Dell have HPC roots — HPE through its Cray lineage, Dell through its PowerEdge and HPC Solutions division — and they're both watching quantum computing hardware mature to the point where it's starting to look like an accelerator you'd attach to a classical system, rather than a standalone island. The question is, how do you actually connect these things? And that's where it gets interesting from a fabric perspective. Skyler: The current reality is that quantum processing units — QPUs — are not plug-and-play. They operate at millikelvin temperatures, they have extremely limited qubit counts relative to the problem sizes classical systems handle, and the latency to get data in and out is significant. So the integration model right now is more like a loosely coupled co-processor than anything resembling a tightly coupled accelerator. Think of it less like a GPU over NVLink and more like a specialized node you offload a very specific subroutine to over a classical network interface. Skyler: HPE in particular has been leaning into this with its Cray EX platform, which already has a pretty sophisticated fabric story around Slingshot. The idea is that you can have a heterogeneous job scheduler that knows about quantum resources the same way it knows about GPU nodes or CPU nodes — it's a resource in the workload manager, you queue for it, you get access. Dell's angle is somewhat similar but more focused on the integration and services layer — making it easier for HPC shops to consume quantum as a cloud service attached to their on-prem classical infrastructure. Skyler: What I find most interesting about this from a fabric standpoint is that nobody has solved the low-latency QPU interconnect problem yet. The classical-to-quantum handoff today is slow enough that it only makes sense for workloads where the quantum speedup is massive — things like quantum chemistry, certain optimization problems, some machine learning kernel work. But as qubit counts and coherence times improve, that calculus changes, and the interconnect question becomes much more urgent. Skyler: For now, both HPE and Dell are essentially building management planes and orchestration frameworks that can accommodate quantum resources, betting that the physics will catch up. It's a smart hedge. And for those of us watching the fabric space, this is a signal to start thinking about what a quantum-aware interconnect standard might eventually look like — because right now, there isn't one. Skyler: Story two — and this one is directly in the CXL wheelhouse, which I know a lot of you track closely. Everspin Technologies just demonstrated a CXL-connected MRAM memory expansion module, and this is a meaningful data point for the CXL memory ecosystem. Skyler: So quick background for anyone newer to MRAM — Magnetoresistive RAM is a non-volatile memory technology. It's persistent like NAND flash, but it has latency characteristics that are much closer to DRAM. It's faster than flash, it has better endurance than flash, and it doesn't need a battery-backed buffer to protect writes. The tradeoff historically has been density and cost — you can't pack as many bits per die as you can with DRAM or NAND. Skyler: What Everspin is doing here is attaching their MRAM to a CXL interface, specifically CXL 2.0, and positioning it as a memory expander. The idea is that you'd sit this behind a CXL switch or directly on the CXL fabric of a host, and it presents as a memory pool that the host can address. Because MRAM is non-volatile, you get persistence semantics — data survives a power cycle — without the write penalties you'd take with flash-backed approaches. Skyler: From a datacenter architecture standpoint, this is interesting for a few specific use cases. Anything where you need byte-addressable persistent memory with low latency — think database logging, checkpoint-restart for long-running HPC or A I training jobs, in-memory data structures that need to survive failures. The Intel Optane experiment showed there's real demand for this tier, and Optane's exit left a gap that people have been trying to fill. Skyler: CXL is the right interface for this. It gives you the coherency semantics and the memory-semantic access that makes persistent memory actually useful versus just fast storage. And Everspin is a real company with shipping MRAM silicon — this isn't vaporware. They make STT-MRAM, which is spin-transfer torque MRAM, and they've been shipping it into industrial and automotive applications for years. Skyler: The challenge for Everspin is scale. To compete in the datacenter memory tier, you need density. Their current parts top out at 1 gigabit per die, which is nowhere near DRAM density. But the CXL demo is a proof of concept for the integration, and it signals that Everspin is serious about pursuing this market as CXL infrastructure matures. Skyler: For those watching CXL — and you should be — this is another data point showing that the ecosystem is filling in around the standard. You've got DRAM expanders, you've got computational storage, and now you've got MRAM-based persistent memory. CXL is becoming the universal memory fabric interface, which is exactly what the architects intended. Skyler: Story three now — EE Times ran a piece called "The Battle to Scale Up the A I Data Center," and while it covers a lot of ground, I want to use it as a hook to talk about the systemic challenges that are shaping every decision in this space right now, because I think it frames a lot of the other stories we're covering today. Skyler: The core tension is pretty simple to state but brutal to solve. A I training and inference workloads are scaling faster than the infrastructure to support them. We're not just talking about compute — GPUs and accelerators are actually improving pretty rapidly. The bottleneck is everything around the compute: power delivery, cooling, and most critically for this show, interconnect bandwidth. Skyler: The scaling problem has two main axes. First, you've got scale-up — that's the fabric inside a single training cluster, connecting GPUs to each other and to memory at high bandwidth and low latency. This is where NVLink, UALink, and InfiniBand all compete. Second, you've got scale-out — that's connecting racks to racks, pods to pods, potentially datacenter to datacenter. This is where Ethernet, InfiniBand, and increasingly, emerging standards like UEC are fighting it out. Skyler: The EE Times piece highlights that the industry is hitting a wall on both fronts simultaneously. For scale-up, the bandwidth density requirements are getting to the point where traditional electrical signaling inside a server or a rack can't keep up — you're running into signal integrity limits, power limits, and just physical space limits. That's pushing co-packaged optics and silicon photonics into the conversation for scale-up fabric, which was almost unthinkable two or three years ago. Skyler: For scale-out, the challenge is that the standard Ethernet and InfiniBand ecosystems were designed around different workload assumptions than what A I training demands. A I training has extremely tight collective communication patterns — all-reduce, all-to-all — that create very bursty, correlated traffic. Standard TCP/IP congestion control doesn't handle this well, and that's been a driver behind the push for things like RDMA, RoCE, and now UEC. Skyler: UEC — the Ultra Ethernet Consortium — is still evolving its spec, and I want to be clear about that. The 1.0 spec has been published, but implementation and interoperability testing is still early. We don't have a mature, multi-vendor UEC ecosystem yet. That's coming, but it's not here. So when you hear hyperscalers talking about UEC as the answer to scale-out A I fabric, they're also making a bet on a standard that's still maturing. Skyler: The broader point from the EE Times piece is that nobody has a clean end-to-end solution right now. Every major hyperscaler is making different bets — some are going heavier on InfiniBand, some on RoCE-based Ethernet, some are building fully custom fabrics. And the equipment vendors — your Aristaes, your Junipers, your Ciscos, plus the newer entrants like Innovium and Oxide — are all positioning for what they think the winning architecture looks like. This is a genuinely open fight. Skyler: Okay, story four — Marvell published a piece making the case for co-packaged optics as, quote, "powering the next wave of A I datacenter innovation." Now, Marvell has a dog in this fight — they're a significant player in optical DSPs and silicon photonics — so read this as a vendor advocacy piece. But the technical arguments are sound, and it's worth unpacking why CPO is getting so much attention right now. Skyler: Co-packaged optics means integrating the optical transceivers directly into the switch package, rather than having pluggable modules that connect to the switch ASIC over a copper trace on a PCB. That sounds like a packaging detail, but the implications are significant. When you move optical conversion off the pluggable module and right up against the switch silicon, you eliminate the copper reach between the ASIC and the optics, which lets you run at lower voltage and lower power per bit. At 800 gig and 1.6 terabit speeds, that power delta is not trivial. Skyler: Marvell's pitch is essentially that CPO is the only path to economically scaling A I fabric bandwidth at the speeds we're heading toward. The argument is that pluggable form factors — even OSFP and QSFP-DD at 800 gig — are running into power density limits. A top-of-rack switch with 64 ports of 800 gig pluggables is burning enormous power just in the module interfaces, and that compounds as you go to 1.6 terabit. CPO cuts that optical interface power significantly. Skyler: The counterargument from the pluggables camp is field replaceability. If you co-package the optics and a laser fails or a transceiver degrades, you potentially have to replace the whole switch, not just swap a module. That's a significant operational cost argument, and it's been the main thing holding CPO adoption back. Marvell and others are working on designs that allow some degree of optical element serviceability within the CPO package, but it's an unsolved problem operationally. Skyler: There's also the ecosystem readiness question. Pluggable optics have a massive, mature ecosystem of vendors, testing infrastructure, and interoperability frameworks. CPO is still early — you're talking about a handful of vendors with production-ready designs, and interop is mostly single-vendor or tightly coupled ASIC-to-optics pairings. The ecosystem needs to broaden significantly before hyperscalers will deploy CPO at scale. Skyler: That said, the physics argument is compelling and doesn't go away. At 3.2 terabit and beyond, the power math for pluggables gets really ugly, and CPO becomes less of a nice-to-have and more of a necessity. Marvell is right that CPO is coming — the timing and the transition path are the open questions. I'd expect to see first serious CPO deployments in hyperscale A I clusters within the next two to three years, likely starting with specific high-bandwidth spine links where the power savings are most dramatic. Skyler: And last story for today — Coherent's presentation and progress report from ECOC 2025. For those not familiar, ECOC is the European Conference on Optical Communications, one of the major venues where the optics industry shows its cards on where the technology is heading. And Coherent — formerly II-VI and Finisar rolled into one — is one of the biggest names in optical components and modules. Skyler: What Coherent showed at ECOC covers three areas: their coherent transceiver roadmap, their module portfolio, and their CPO progress. Let me hit each briefly. Skyler: On coherent transceivers — and here "coherent" means the optical modulation technique, not the company name, just to avoid confusion — Coherent is pushing their 400 gig ZR and 400 gig ZR-plus pluggable coherent modules, with 800 gig coherent on the roadmap. Coherent optics are primarily for long-haul and metro interconnect — datacenter-to-datacenter, not within a datacenter. But as hyperscalers build distributed A I clusters across multiple physical sites, coherent DCI — datacenter interconnect — becomes increasingly important to the A I fabric story. Skyler: On the module side, Coherent is covering the full spectrum — 400 gig, 800 gig pluggables, OSFP, QSFP-DD-DCO. They're also pushing into 1.6 terabit module designs. The module portfolio is important because it shows where near-term deployments will actually happen — even as CPO gets all the press, pluggable modules are what's going into datacenters right now and for the next several years. Skyler: The CPO piece is where it gets most interesting for long-term fabric architecture. Coherent is showing CPO designs that integrate their silicon photonics platform directly with switch ASICs. They're working with multiple ASIC partners — they haven't locked into a single relationship — which is strategically smart. They want to be the optical layer regardless of whose switch ASIC wins. Skyler: One thing that stood out from the ECOC coverage is Coherent's emphasis on manufacturing scale. CPO is not just a design problem — it's a packaging and yield problem. Getting photonic integrated circuits to co-exist with switch ASICs at high yield, at volume, with acceptable cost, is a significant manufacturing challenge. Coherent is leaning on their vertically integrated manufacturing footprint — they make their own lasers, their own PICs, their own DSPs — as a differentiator here. That vertical integration gives them more control over the yield and cost equation than competitors who are assembling CPO from third-party components. Skyler: The competitive landscape in CPO is shaping up to be Coherent versus Marvell — who we just talked about — versus a handful of others like Ayar Labs with their optical I/O chiplet approach, and the hyperscalers themselves who are doing internal CPO development. It's early innings, but Coherent's ECOC showing suggests they're serious about being a major player in the datacenter CPO market, not just in their traditional telecom stronghold. Skyler: Alright, that's a wrap on today's show. Five stories, a lot of ground covered — from quantum-classical integration aspirations, to CXL-connected persistent memory, to the systemic scaling battle in A I datacenters, to the CPO transition that's reshaping how we think about switch design and optical interconnect. There's a lot moving right now, and we'll be tracking every bit of it right here. Skyler: Line Rate, brought to you by Ada and Zen Semiconductor. Ada helps organizations actually integrate A I into their workflows in ways that move the needle — worth checking out. If you found today's episode useful, subscribe wherever you get your podcasts, share it with a colleague who needs to know this stuff, and check the show notes for links to all the stories we covered today. I'm Skyler Monroe — catch you next time.