Coherent Stock: A Buy Driven By Robust AI Datacenter Optics Demand (NYSE:COHR) - Seeking Alpha

Skyler: Hey, welcome to Line Rate — the show where we dig into the chips, cables, standards, and companies that move data at the speed that A I demands. I'm Skyler Monroe, and if it touches datacenter fabric, high-speed interconnect, or the optics holding it all together, we're talking about it here. Big thanks to our sponsors today — Ada, who helps organizations actually integrate A I into their real workflows, and Zen Semiconductor, an umbrella company with a portfolio of companies across the silicon industry. Alright, we've got a packed show today — optics stocks, Cisco going full-stack, AMD dropping a new networking chip, Ciena making the case for hyper-rail photonics, and what it actually takes to get to 1.6 terabits per second interoperability. Let's get into it. Skyler: First up — Coherent. If you've been watching the optics space, you know the name. Seeking Alpha just ran a pretty bullish piece on Coherent's stock, and the thesis is pretty straightforward: A I datacenter build-outs are driving a structural surge in demand for high-speed optical transceivers, and Coherent is one of the few companies with the portfolio breadth and manufacturing scale to actually capture that wave. So let's unpack why that matters technically, not just from an investment angle. Skyler: Coherent plays across a huge range of the optics stack — from the indium phosphide lasers and the epitaxial wafers all the way up to finished 400G, 800G, and now 1.6T transceiver modules. That vertical integration is actually a big deal right now because the supply chain for high-speed optics is genuinely stressed. When you're building out a hundred-thousand-GPU cluster, you're not just buying a handful of transceivers — you're talking about hundreds of thousands of 400G or 800G QSFP-DD or OSFP modules just for the GPU-to-switch fabric tier alone, and then another massive slug for the spine and for anything going out to external connectivity. Skyler: What's pushing Coherent specifically into the spotlight is the transition happening right now from 400G to 800G as the baseline for AI fabric, and the early innings of 1.6T starting to show up in design wins. Each generational jump roughly doubles the DSP complexity, the laser precision requirements, and the thermal challenges. Coherent has been investing heavily in its vertical cavity surface emitting laser — VCSEL — and edge-emitting laser capacity, and that's paying off as hyperscalers qualify vendors for next-generation builds. Skyler: The other piece that the Seeking Alpha analysis touches on is co-packaged optics — CPO. This is still a few years out from broad deployment, but Coherent is positioning itself to be a key supplier there too. CPO fundamentally changes where the optical engine lives — instead of a pluggable module hanging off the front panel, the optics get integrated directly onto the switch package or very close to it. That cuts the electrical trace lengths dramatically and gets you better power efficiency at 1.6T and beyond. The risk for Coherent is that CPO could eventually commoditize some of the module business that's their bread and butter today, but being inside the CPO ecosystem at the component level is actually a smart hedge. Skyler: From a competitive standpoint, Coherent is up against II-VI — which they actually acquired — as well as Lumentum, Fabrinet on the manufacturing side, and a wave of Chinese suppliers like Accelink and InnoLight that are increasingly competitive on 400G pricing. The bull case is that at 800G and 1.6T, qualification cycles are long, customer relationships matter, and Coherent's depth of vertical integration gives them a defensible position. Whether that shows up in the stock is a different question — but the underlying demand signal is very real. Skyler: Okay, next story — Cisco. Cisco put out a blog post this week about what they're calling their full-stack A I-ready datacenter solution, bundling compute, networking, and security under a unified architecture. Now, I'll be honest — vendor blog posts are vendor blog posts, and you have to read between the lines a bit. But there's actually something substantive here worth unpacking, especially for the architects in the audience. Skyler: The core claim Cisco is making is that A I workloads break traditional datacenter network assumptions in some pretty fundamental ways. Traditional east-west traffic in a web-scale datacenter is bursty and relatively forgiving — you get a TCP flow, it backs off, it recovers. A I training traffic, especially with collective communication operations like all-reduce, is synchronized and extremely latency-sensitive. If one flow in an all-reduce stalls, the whole GPU collective stalls. Cisco is positioning their networking stack — specifically their Nexus switches running at 400G and 800G — as optimized for that traffic pattern. Skyler: What Cisco is leaning into is their telemetry and visibility story, which is actually underrated in the A I fabric conversation. When you're debugging a degraded training run, you need to know with very fine granularity where the congestion is, which flows are dropping, what the queue depths look like at every hop. Cisco's done real work on streaming telemetry and their network assurance tooling, and that matters operationally even if it doesn't show up in a raw bandwidth spec. Skyler: The security angle is interesting and a little surprising in a purely networking context, but it makes sense when you think about what's actually running in these clusters. A I training clusters are increasingly running multi-tenant or multi-team workloads, and the model weights and training data sitting in those clusters are genuinely valuable. Pervasive security — meaning security policy that follows workloads across the fabric rather than being bolted on at the perimeter — is a real architectural challenge and Cisco is positioning their intent-based networking and microsegmentation capabilities as the answer. Skyler: Where I'd push back a little is on the competitive positioning. The hyperscalers are mostly building their own fabrics — Google's building TPU pods with custom interconnect, Meta has its A I Research SuperCluster with Arista and custom gear, Microsoft is investing in their own optics. The market Cisco is really going after is the enterprise and mid-market — the companies standing up on-prem A I infrastructure who want a full-stack answer from a single vendor with a support contract. For that buyer, a Cisco full-stack pitch actually makes a lot of sense, even if it's not what a tier-one cloud is going to deploy. Skyler: The big question hanging over Cisco's A I infrastructure story is where they land in the InfiniBand versus Ethernet debate, which brings us perfectly to the next story. Skyler: AMD dropped some details on Helios this week, and it's a significant move. Helios is AMD's new A I networking ASIC, and the headline is that AMD is betting hard on open Ethernet — specifically Ultra Ethernet Consortium, U E C — rather than InfiniBand. This is AMD explicitly planting a flag in the Ethernet camp at a moment when that choice is genuinely contested. Skyler: Let me give some context on why this matters. InfiniBand — specifically NVIDIA's HDR and NDR InfiniBand with their ConnectX NICs and Quantum switches — has been the dominant fabric for high-performance A I training clusters for the better part of a decade. The reason is RDMA — remote direct memory access — and the congestion control and collective communication offload capabilities that NVIDIA has built into that stack. When you're doing a hundred billion parameter model training run, the interconnect fabric is on the critical path for every gradient synchronization step. Skyler: Ethernet has historically lagged InfiniBand in those latency and collective communication characteristics, but that gap has been closing, and U E C is specifically designed to close it the rest of the way. U E C is a set of extensions being developed by the Ultra Ethernet Consortium — which includes AMD, Intel, Cisco, Arista, Meta, Microsoft, and others — targeting low-latency, lossless transport optimized for A I workloads. We're talking congestion control, out-of-order packet handling, and eventually collective communication acceleration — all built on top of standard Ethernet. Skyler: AMD's Helios ASIC is designed to implement those U E C capabilities in hardware. The Fierce Network piece notes that AMD is positioning this not just for their Instinct GPU line but as a broadly deployable solution — meaning they'd like to see Helios or Helios-derived silicon in other vendors' systems as well. That's an interesting business model angle — AMD potentially as a networking silicon vendor, not just a compute vendor. Skyler: Now — important caveat — U E C specs are still actively evolving. The consortium has published some preliminary specs, but we are not yet at the point where you have fully interoperable U E C gear shipping at scale. AMD is making a forward bet here. Helios is real, the engineering is real, but the ecosystem it's betting on is still being built. The risk is that InfiniBand maintains its latency and software-stack advantages long enough that the Ethernet camp has trouble gaining traction in the highest-performance training clusters even as it wins on cost in inference and at scale-out tiers. Skyler: The competitive dynamics here are fascinating. NVIDIA obviously has an enormous interest in defending InfiniBand — they own Mellanox, they make the NICs and the switches and the software stack. Every workload that shifts to Ethernet is a workload that doesn't need an NDR InfiniBand switch from NVIDIA. That's exactly why the Ultra Ethernet Consortium has the lineup of members it does — these are companies that would very much like to commoditize the interconnect layer and not pay the NVIDIA tax on the fabric. Skyler: Watch the hyperscaler signals here. If you see Meta or Microsoft or Google start qualifying U E C-based gear for training clusters — not just inference — that's when you know the Ethernet story has legs for the hardest workloads. Until then, it's a very promising bet, but InfiniBand is still the safe choice for production training at the frontier scale. Skyler: Alright, let's talk about Ciena and hyper-rail photonics. Ciena — better known for their long-haul and metro optical networking gear — published a piece making the case that their hyper-rail photonic architecture is the right answer for next-generation datacenter fiber infrastructure. This is an interesting one because Ciena is pushing into a space that's traditionally been dominated by companies like Arista, Cisco, and the transceiver vendors on the intra-datacenter optics side. Skyler: So what is hyper-rail? At its core, it's a photonic architecture that uses wavelength division multiplexing — WDM — inside the datacenter rather than just in the wide area or metro. Traditional datacenter fiber runs one signal per fiber — you put in a pluggable transceiver, you get one 400G or 800G lane per strand of fiber. Hyper-rail stacks multiple wavelengths onto a single fiber using DWDM or CWDM4, multiplying the capacity you can extract from existing fiber plant. Skyler: Why does this matter now? Because the fiber infrastructure inside large datacenters and between datacenter buildings on a campus is becoming a genuine bottleneck. When you're building a cluster at the scale of a hundred thousand GPUs, the fiber count gets enormous fast, and pulling new fiber — especially inside a building — is expensive, slow, and sometimes physically impossible given conduit fill. If you can get 8x or 16x more capacity out of each fiber strand by going to WDM, that's a massive win for infrastructure density and economics. Skyler: Ciena's angle is that their coherent optical technology — the kind they've refined over years in long-haul networks — can be adapted to shorter reach inside the datacenter and campus. The tradeoff historically has been power and cost — coherent optics consume significantly more power than a standard pluggable transceiver, and the DSP complexity drives up cost. Ciena is arguing that at the capacity levels A I clusters demand, the economics flip — you pay more per port but you use vastly less fiber and conduit infrastructure, and the total cost of ownership pencils out. Skyler: This connects back to the co-packaged optics conversation we had in the Coherent segment. CPO and hyper-rail photonics are solving different but related problems. CPO is about getting bandwidth density up at the switch chip interface. Hyper-rail is about maximizing what you can push through each fiber strand across longer intra-datacenter runs. In a fully built-out A I datacenter at scale, you probably need both. Skyler: The competitive question for Ciena is execution — can they productize this for the datacenter buyer, who has very different procurement and operational expectations than a telecom carrier? Datacenter operators want pluggable, standard, easy to swap. Ciena's traditional sweet spot is high-touch engineered solutions. That's a cultural and product challenge as much as a technical one. But the photonic density problem they're pointing at is real and growing, and if they can crack the productization, it's a legitimate market. Skyler: Last story, and honestly one of the more technically meaty pieces this week — Semiconductor Engineering ran a deep dive on system-level design for 1.6 terabits per second interoperability in A I datacenters. This is the kind of article that gets forwarded around signal-integrity and photonics engineering teams, and for good reason — 1.6T is where things get genuinely hard. Skyler: Let's set the stage. The industry is mid-transition from 400G to 800G as the fabric baseline right now. 1.6T is the next step, and it's not just twice the bandwidth of 800G — it's a qualitatively different engineering challenge at almost every layer of the stack. You're pushing electrical signals at 112 gigabaud PAM4 or moving to 224 gigabaud, the fiber and connector tolerances get tighter, thermal dissipation on the ASIC gets harder, and the DSP power budgets are increasingly constrained. Skyler: The Semiconductor Engineering piece focuses on what interoperability actually means at 1.6T, which is a subtle but critical point. At lower speeds, you could often get away with proprietary implementations that happened to talk to each other. At 1.6T, the signal integrity margins are tight enough that you need very precise agreement on forward error correction — FEC — schemes, electrical interface specs, and the optical link budget. The industry bodies doing this work include the IEEE 802.3 working groups and the Optical Internetworking Forum — OIF — and those specs are still being hammered out. Skyler: One of the key tensions the article highlights is between electrical and optical connectivity. At 1.6T, the case for moving the optical engine closer to the ASIC — again, this is the CPO argument — gets much stronger because the channel loss on a long PCB trace at 224 gigabaud is severe. You're either adding a lot of retimer complexity and power to deal with that loss, or you're shortening the electrical path by putting the optics closer to the die. Skyler: The interoperability challenge is also a multi-vendor problem in a way that lower speeds weren't. A 1.6T end-to-end link might involve a switch ASIC from Broadcom or Marvell, a DSP retimer from one vendor, an optical engine from another, and a cable or fiber from yet another. Each of those interfaces has to be specified tightly enough that you can mix and match, and the industry is still working out exactly where those interfaces standardize. Skyler: The UCIe and co-design conversations are relevant here too — as you push signaling speeds up, the boundary between the chip package, the optical engine, and the connector becomes blurry in really interesting ways. Some of what we think of as a transceiver today might partially migrate onto the package or into the substrate. The Semiconductor Engineering piece does a good job of laying out the design space without pretending the standards are more settled than they are, which I appreciate. Skyler: The practical takeaway for architects and engineers is this — if you're designing infrastructure that you expect to run for five to seven years, you need to be thinking about 1.6T upgrade paths right now, even if you're buying 400G or 800G today. The fiber plant you install, the conduit fill you leave, the power and cooling headroom you provision — all of that shapes whether a 1.6T upgrade is a swap or a rebuild. And in A I infrastructure, the cost of a rebuild because someone didn't plan for it is very, very real. Skyler: Alright, that's a wrap on this week's Line Rate. We covered Coherent's optics position and why A I is a structural demand driver, Cisco's full-stack datacenter push and what it actually means for the enterprise buyer, AMD's Helios bet on Ultra Ethernet and where U E C stands today, Ciena's hyper-rail photonics case for WDM inside the datacenter, and what 1.6T interoperability actually requires at the system level. A lot happening, as always, in this space. Skyler: Thanks to our sponsors — Line Rate, brought to you by Ada and Zen Semiconductor. Ada helps organizations integrate A I into their real workflows, and Zen Semiconductor is an umbrella company with a portfolio across the silicon industry. If you found this useful, subscribe wherever you get your podcasts and share it with someone on your team who needs to stay sharp on A I infrastructure. Full show notes with links to everything we covered are in the episode description. See you next week.