Arista gets into scale-up game as accelerator landscape diversifies - Fierce Network

Skyler: Hey, welcome back to Line Rate — the show that keeps you current on datacenter fabric, AI interconnect, and the standards and silicon moving data at scale across the modern AI infrastructure stack. I'm Skyler Monroe, and I've been deep in the weeds this week so you don't have to be. Quick thanks to our sponsors: Ada, who helps organizations actually integrate A I into their real workflows, and Zen Semiconductor, an umbrella company with a portfolio of businesses across the silicon industry — including Ada on the A I deployment side. Alright, we've got a packed episode today: Arista stepping into the scale-up game, Synopsys throwing its weight behind U E C and U A Link IP, a new piece on the so-called third dimension of A I networking, the hyperscalers making a joint connectivity announcement, and Ayar Labs closing a massive funding round. Let's get into it. Skyler: So first up — Arista Networks, a company most of you know as the dominant force in scale-out Ethernet switching for AI clusters, is now planting a flag in scale-up networking. This is a meaningful pivot worth unpacking, because scale-up and scale-out are fundamentally different problems. Skyler: Quick level-set for anyone who needs it: scale-out is what you're doing when you connect hundreds or thousands of GPUs across a spine-and-leaf Ethernet fabric — think the big flat networks that move gradients and activations between nodes. Scale-up is the tighter, lower-latency, higher-bandwidth interconnect that stitches together the accelerators within a single node or a small pod — think NVLink, or the kinds of links U A Link is targeting. Skyler: Arista's move here is interesting because the accelerator landscape is genuinely diversifying. For a long time, if you were talking scale-up, you were basically talking NVIDIA and NVLink, full stop. But now you've got a whole generation of custom silicon — hyperscaler TPUs, Trainium, Gaudi, and a wave of AI chip startups — that need a scale-up story that isn't proprietary to one vendor. Skyler: That's the opening Arista is walking through. As more accelerator vendors come to market without a baked-in scale-up fabric, there's a real need for a standards-based, interoperable approach. And Arista has the relationships, the software stack, and the Ethernet DNA to make a credible play here. Skyler: The timing also lines up with where U A Link is in its maturity curve. The U A Link Consortium has been building momentum — we'll talk about that more in a minute — and an Arista presence in the scale-up space could be a nice complement to U A Link adoption, even if Arista isn't explicitly tied to that spec yet. Skyler: What I'd be watching here is how Arista positions against the proprietary fabrics. NVLink isn't going anywhere for NVIDIA-heavy deployments, but in a mixed or open-accelerator environment, the pitch for a more open, Ethernet-adjacent scale-up play gets a lot more compelling. Arista knows how to play the long game on ecosystem, and this feels like them getting positioned early before the market solidifies. Skyler: The other thing worth noting is that Arista entering this space sends a signal to the rest of the industry. When a company with Arista's market credibility decides the scale-up space is big enough to compete in, that's a validation that the market is real and growing — not just a hyperscaler science project. Skyler: Alright, story two — Synopsys is announcing that it's going to launch IP solutions targeting both Ultra Ethernet and U A Link. And this one is genuinely important because it's about the plumbing that makes standards real. Skyler: Let's back up a second. Ultra Ethernet — or U E C, the Ultra Ethernet Consortium spec — is a standards effort to adapt Ethernet for the specific demands of AI and HPC workloads. Traditional Ethernet wasn't designed with the congestion sensitivity and latency requirements that large-scale distributed training has, so U E C is addressing things like transport behavior, packet ordering, and reliability in a way that's tuned for AI fabric. Skyler: U A Link is a separate but related effort — it's targeting the scale-up layer specifically, the high-bandwidth low-latency links between accelerators within a tightly coupled pod or node. Think of it as a potential open alternative to proprietary scale-up interconnects. Skyler: Now here's the thing about standards: a spec document is not a product. Standards become real when chip companies and system builders can actually implement them, and that's where silicon IP vendors like Synopsys come in. When Synopsys says they're building verified, production-grade IP blocks for U E C and U A Link, that dramatically lowers the cost and time-to-market for any fabless chip company that wants to support these standards. Skyler: Without something like this, every accelerator startup that wants to support U E C has to either license IP from someone who has it, build it themselves — which is enormously expensive and risky — or wait for the ecosystem to mature. Synopsys stepping in and commercializing IP for both standards is an ecosystem accelerant. It's the kind of move that turns a consortium spec into something you can actually tape out to. Skyler: Synopsys also has an existing relationship with basically every serious chip company on the planet through their EDA and IP businesses, so the distribution here is real. This isn't a startup making a bet on an unproven standard — this is a tier-one IP vendor making a commercial bet that U E C and U A Link are going to matter, and betting early enough to be the go-to source when the designs ramp. Skyler: I'd keep an eye on Cadence's response here, because you can bet they're looking at the same opportunity. And the more IP vendors support these standards, the faster we get competitive, interoperable silicon in the market — which is ultimately what the whole consortium ecosystem needs. Skyler: The fact that Synopsys is covering both U E C and U A Link is also interesting — it suggests they see these as complementary parts of the same AI fabric story, which I think is the right read. Scale-out and scale-up aren't competing, they're layered. Skyler: Story three comes from Futurum Group, and it's a framing piece that I think is actually worth engaging with — they're calling geo-distributed or campus-to-campus connectivity the "third dimension" of A I infrastructure design. Scale-up, scale-out, and now scale-across. Skyler: The basic argument is that as AI workloads get larger and as hyperscalers and large enterprises spread compute across multiple datacenters — either for capacity, resilience, or power constraints — the interconnects that stitch those datacenters together become a first-class design concern, not an afterthought. Skyler: This is not a crazy framing. We're already seeing evidence of this in the wild. The reason Microsoft, Google, and others have been investing heavily in coherent optical, DCI — datacenter interconnect — and even submarine cable infrastructure isn't just about internet traffic. It's increasingly about moving AI model state, checkpoint data, and even live training traffic across geographic boundaries. Skyler: The latency and bandwidth envelope for scale-across is obviously very different from scale-up or even scale-out. You're dealing with fiber-speed latencies — hundreds of microseconds to milliseconds — rather than the sub-microsecond world of NVLink or U A Link. So the protocols, the transport assumptions, and the hardware are all different. Skyler: Where this gets technically interesting is in the software and systems layer. How do you partition a training job or inference pipeline in a way that tolerates the latency of a WAN link? What does checkpoint synchronization look like when your accelerator pods are fifty miles apart? These are hard problems, and the answer involves both better interconnect hardware and smarter orchestration. Skyler: From a standards perspective, this is still pretty nascent. U E C and U A Link are focused on the intra-datacenter world. The scale-across layer is mostly being addressed through proprietary DCI solutions right now — coherent DWDM, dedicated fiber, custom routing protocols. There's not a clear open-standards analog yet for this layer the way U E C is trying to be for the Ethernet fabric. Skyler: I think the "three dimensions" framing is a useful mental model for architects, even if the third dimension is less standardized and more bespoke right now. The implication for our audience is: if you're designing AI infrastructure and you're only thinking about the intra-rack and intra-datacenter layers, you may be missing a growing piece of the cost and complexity picture. Skyler: Story four — and this is the one that probably generated the most headlines this week — Microsoft, Meta, and Google have jointly announced a new A I connectivity standard for datacenters. And yes, when those three names show up together on a press release, you pay attention. Skyler: Now, the coverage on this has been a bit vague on specifics, so let me give you the context that matters. This announcement is almost certainly tied to the Ultra Ethernet Consortium and the broader push to standardize the transport and signaling layers for AI workloads on Ethernet. These three companies are all members of U E C, and a joint announcement from them signals a level of hyperscaler alignment that the spec hasn't always had. Skyler: Why does hyperscaler alignment matter? Because these are the companies that buy hundreds of thousands of ports, build their own ASICs, and have the purchasing power to make or break a standard. When Microsoft, Meta, and Google agree on something, the supply chain listens. Switch vendors, NIC vendors, and silicon IP providers all start prioritizing that roadmap. Skyler: The interesting competitive angle here is what's not in the announcement — specifically NVIDIA and Broadcom. NVIDIA has NVLink for scale-up and is a complicated player in scale-out given they acquired Mellanox. Broadcom is the dominant merchant silicon vendor for Ethernet switching but has its own set of interests. A strong hyperscaler coalition pushing an open standard creates pressure on both of those incumbents. Skyler: It's also worth noting that U E C as a spec is still evolving. The transport layer work — which covers things like packet spraying, congestion notification, and retransmit behavior — is real and has substance, but we haven't seen mass production deployments at scale yet. Announcements like this are how you build the industry confidence to get there. Skyler: One thing I'd flag: "new connectivity standard" is a bit of an overstatement if this is an endorsement of existing U E C work rather than a genuinely new spec. But from a market-signaling perspective, it almost doesn't matter. The message to the industry is: these three hyperscalers are aligned, they want open and interoperable AI fabric, and they're willing to put their names on it publicly. That's a big deal regardless of the headline framing. Skyler: Watch for the follow-on: which vendors announce U E C-compliant products in the next one to two quarters. That's where you'll see the real impact of this kind of announcement. Skyler: And finally — Ayar Labs has closed a 650 million dollar funding round, making it one of the best-capitalized optical interconnect startups on the planet. Let's talk about why this is significant and what they're actually building. Skyler: Ayar Labs is one of the leading players in co-packaged optics — specifically, they're working on in-package optical I/O, where the optical transceiver is integrated directly with the compute or switching chip at the package level rather than sitting at the edge of a PCB as a pluggable module. Their TeraPHY chiplet is the core product — it brings optical I/O onto the same package as an ASIC or GPU. Skyler: The reason this matters for AI fabric is bandwidth density and power. As AI clusters scale, the number of high-speed electrical lanes you need to get data off a chip explodes, and SerDes — the high-speed electrical signaling that drives pluggable optics — burns a lot of power and has real signal integrity constraints at high data rates. Co-packaged optics moves the optical conversion much closer to the chip, shortening the electrical path dramatically and enabling much higher bandwidth per watt. Skyler: 650 million dollars is a lot of money, and it tells you a few things. First, the investors — which reportedly include major strategic backers — believe that co-packaged optics is going to be a mainstream technology in AI infrastructure, not a niche play. Second, the capital requirements for scaling optical chiplet production are enormous. You're dealing with wafer-level photonics, chip-to-chip integration challenges, and yield issues that take real money to solve. Skyler: Ayar isn't the only player here. Ranovus, Celestial AI, and others are working on related approaches, and all of the major hyperscalers have internal programs around co-packaged or near-package optics. Intel has been working on silicon photonics for years. So it's a competitive space. Skyler: But Ayar has a specific angle that's differentiated: they're using a commercial foundry process for their photonics — GlobalFoundries — rather than building a custom photonics fab, which gives them a more scalable manufacturing path than some competitors. And the TeraPHY chiplet approach is designed to be interoperable with different host chips, which is important if you want broad adoption. Skyler: The 650 million dollar raise also positions Ayar to survive the long sales cycles that come with getting designed into hyperscaler ASICs and merchant switch silicon. These design wins take years, and you need the runway to outlast the development cycle. This round gives them that. Skyler: What I'd be watching is customer announcements — actual design wins or pilot deployments. Funding is great, but the signal that really matters is when a hyperscaler or a tier-one switch vendor says Ayar technology is in the critical path of their next-generation fabric. At 650 million dollars raised, that announcement is probably coming, and when it does, it'll be a big moment for the co-packaged optics field. Skyler: Alright, that's a wrap on this week's Line Rate. Arista into scale-up, Synopsys commercializing U E C and U A Link IP, the third dimension of AI networking, hyperscaler alignment on open connectivity standards, and Ayar Labs closing one of the biggest rounds in optical interconnect history. A lot of pieces moving at once, and they're all connected — the industry is building toward an open, high-bandwidth, power-efficient AI fabric stack, and this week showed several more foundations getting laid. Skyler: Big thanks to our sponsors — Ada, who helps teams actually integrate A I into their real workflows and get value from it, and Zen Semiconductor, an umbrella company with a portfolio across the silicon industry. Line Rate, brought to you by Ada and Zen Semiconductor. Skyler: If you found this useful, please subscribe wherever you get your podcasts, and share it with a colleague who's trying to track this space — there's a lot of noise out there and I'm trying to be the signal. Show notes with links to all the stories we covered today are in the episode description. I'll see you next week.