Don’t bring yesterday’s optics to tomorrow’s AI fabric - Data Center Dynamics

Skyler: Hey, welcome to Line Rate — the show about datacenter fabric and A I high-speed interconnect. I'm Skyler Monroe, and if you care about the silicon and standards moving data between accelerators, across racks, and between datacenters, you're in the right place. Big thanks to our sponsors: Ada, which helps organizations actually integrate A I into their real workflows, and Zen Semiconductor, an umbrella company with a portfolio of businesses across the silicon industry. Today we've got optics all over the place — next-gen packaging, 1.6 terabit interoperability challenges, and Marvell showing up with some serious 2nm photonics muscle. Let's get into it. Skyler: Alright, first up — Data Center Dynamics ran a piece with a title that pretty much says it all: "Don't bring yesterday's optics to tomorrow's A I fabric." And honestly, as a thesis statement for where this industry is right now, I couldn't have said it better myself. Skyler: So what's the core argument here? The piece is essentially a warning shot to operators and architects who are still thinking about optical interconnects the way they did two or three years ago — when you were mostly worried about spine-leaf connectivity, 400G ports, and conventional pluggable modules. That world is not the world you're building in anymore. Skyler: When you move into dense A I fabric — think GPU clusters at scale, NVL-style rack architectures, or the kind of east-west traffic patterns you get inside a large training job — the assumptions just break. Latency budgets tighten dramatically. Power per bit becomes a first-class constraint, not an afterthought. And the sheer port density you need to keep thousands of accelerators fed means your old pluggable economics just don't hold up. Skyler: The piece makes a distinction that I think is really important for architects to internalize: there's a difference between optics that were designed for general-purpose networking and optics that are being co-designed with the A I fabric itself. And the gap between those two things is widening fast. Skyler: What "yesterday's optics" looks like in practice is your conventional pluggable form factors — your QSFP-DD, your OSFP — sitting in a switch or a line card, doing 400G or 800G, hot, power-hungry, and physically separated from the ASIC by a meaningful PCIe or SerDes hop. That hop has a cost. It's not free. And at the speeds we're talking about now — 1.6 terabits per port moving into 3.2T on the roadmap — that cost becomes a serious design constraint. Skyler: What "tomorrow's optics" looks like is closer integration. Near-package optics, co-packaged optics, eventually on-chip photonics. The signal path gets shorter, power goes down, and you can actually hit the bandwidth density that next-generation A I clusters need. The piece is essentially arguing: if you're building infrastructure today that will be in production in 18 to 24 months, you need to be designing around where optics are going, not where they've been. Skyler: And the competitive angle here is real. Hyperscalers who get this transition right — who co-design their optical layer with their fabric topology — are going to have a meaningful efficiency advantage over operators who are still bolting on pluggables and hoping the power budget works out. This is one of those infrastructure decisions that looks tactical but is actually strategic. Skyler: Next story, and we're staying in A I fabric but shifting from optics to the scale-up network layer specifically. Marvell published a piece on scale-up network solutions for A I infrastructure, and there's a lot to unpack here because "scale-up" is a term that gets thrown around a lot but doesn't always get defined carefully. Skyler: So let me set the table. In the A I cluster world, you have two distinct network domains that have very different requirements. Scale-out is your traditional high-performance computing network — it's the fabric connecting nodes across a cluster, moving gradients during distributed training, handling collective operations across potentially thousands of GPUs. Ethernet and InfiniBand live here. Ultra Ethernet Consortium is trying to rethink what Ethernet looks like in this space. Skyler: Scale-up is different. Scale-up is the interconnect that keeps a single logical compute unit coherent — it's what lets you treat, say, eight or sixteen or thirty-two accelerators as a single large processor. NVLink is the canonical example here. PCIe at close range is another. The latency requirements are tighter, the bandwidth density is higher, and the topology is usually much more constrained — you're not doing arbitrary routing, you're doing a defined physical graph. Skyler: Marvell's angle here is that scale-up is increasingly a product opportunity, not just a captive in-house technology. Historically if you wanted high-performance scale-up interconnect, you were buying it from whoever made your GPU. That's changing. As more hyperscalers build custom A I accelerators, as more startups build inference chips, the demand for merchant silicon that can handle scale-up interconnect is growing. Skyler: What Marvell is pitching is essentially: we can give you a scale-up fabric that isn't tied to one vendor's accelerator ecosystem. That matters a lot if you're a hyperscaler building a custom training chip and you want to define your own interconnect topology rather than licensing someone else's. It matters for chiplet architectures where you need high-bandwidth low-latency die-to-die or package-to-package links. Skyler: The technical substance involves SerDes at very high lane rates — we're talking 112 gigabaud and pushing toward 224 — combined with the kind of retimer and DSP technology that Marvell has been building for years on the networking side. The pitch is that you can get NVLink-class bandwidth density with merchant silicon and open interfaces. Skyler: The broader competitive picture: this is Marvell competing directly with the vertical integration model that NVIDIA has built with NVLink. Not head-to-head on features today, but on the trajectory. And for anyone building a custom accelerator stack — whether you're a hyperscaler or a well-funded A I chip startup — the ability to source scale-up interconnect from a merchant vendor changes your design space considerably. Skyler: U A Link is also relevant context here. The U A Link consortium — backed by AMD, Intel, Google, Meta, Microsoft, and others — is explicitly trying to define an open scale-up interconnect standard. Marvell's scale-up silicon could sit underneath a U A Link implementation. The standard and the merchant silicon ecosystem are co-dependent, and Marvell knows it. Skyler: Okay, story three — GlobalFoundries just announced something called the SCALE optical module solution, and the pitch is accelerating adoption of co-packaged optics for A I datacenters. This one is interesting because GlobalFoundries is a foundry, not a system company, and foundry-level announcements about optics integration are a signal about where the manufacturing ecosystem is maturing. Skyler: So what is SCALE? GlobalFoundries is positioning it as a platform — a set of process technologies, design rules, and integration approaches — that lets module makers build co-packaged optical solutions on GF silicon. The key capability they're highlighting is tight integration between photonic components and electronic control logic, which is the hard part of co-packaged optics. Skyler: Here's why co-packaged optics is hard, for anyone who hasn't spent time in this rabbit hole. The photonic components — your lasers, your modulators, your detectors — have very different process requirements than your CMOS logic. Historically these have been separate devices that you connect externally. Co-packaging means getting them physically close, ideally in the same package as your switching ASIC or your A I accelerator, so you eliminate the lossy electrical channel between them. Skyler: The benefit is significant: lower power, higher bandwidth density, and better signal integrity at the lane rates we need for next-generation A I fabric. The challenge is that it requires close collaboration between the photonics process, the packaging technology, and the ASIC design. You can't just bolt a photonic chiplet onto an existing ASIC design and call it co-packaged. It has to be co-designed. Skyler: What GlobalFoundries is doing with SCALE is essentially saying: we've done the hard foundry-side work to make this manufacturable at scale, and here's a well-defined interface for module makers and system designers to build on. That's actually really important. One of the historical blockers for co-packaged optics has been yield and manufacturability — the photonics process is finicky, and getting acceptable yield when you're integrating it with expensive ASIC silicon has been a real problem. Skyler: If GF has cracked enough of that problem to offer it as a platform with defined design rules and a qualification process, that dramatically lowers the barrier for module makers to bring co-packaged products to market. And that means more supply, more competition, and faster adoption across the A I fabric space. Skyler: The competitive context here is worth noting. GF is not the only foundry chasing this. TSMC has its own photonics roadmap. Intel has Silicon Photonics as a core competency and has been shipping it in products for years. The race to be the preferred foundry platform for co-packaged optics at datacenter scale is real, and GF staking out a position with a named platform is a clear move in that race. Skyler: For hyperscalers and system architects, the practical implication is: the supply chain for co-packaged optics is developing faster than it was two years ago. The technology isn't fully mature, the ecosystem isn't fully standardized, but the foundry infrastructure is getting built out. Start planning your qualification timelines accordingly. Skyler: Story four, and we're back to Marvell — this time specifically on their 2nm optical technology demonstration for next-generation A I datacenters. This is related to but distinct from the scale-up story, so let me separate them clearly. Skyler: The 2nm angle here is about process node for the photonic and electronic integration. Marvell is demonstrating that you can build optical transceiver technology on a 2nm process node, and the implications of that are pretty significant if you think through the power and density math. Skyler: Every generation of CMOS scaling gives you better energy efficiency for the digital logic that controls your optical components — your DSPs, your forward error correction, your clock and data recovery circuits. Moving that control logic to 2nm from the 5nm or 7nm generation means meaningfully lower power per bit for the electrical side of the transceiver. And in a datacenter where you might have hundreds of thousands of optical ports, that adds up fast. Skyler: But Marvell is doing something more interesting than just shrinking the digital logic. They're integrating silicon photonics with the 2nm process, which is technically much harder than just running your DSP on a new node. Silicon photonics historically has been done on older, larger nodes — 90nm, 130nm — because the waveguide dimensions are set by the wavelength of light, not by transistor scaling. Getting photonics and 2nm CMOS to play together in the same package or on the same die requires real process innovation. Skyler: The demonstration Marvell is showing targets the 1.6 terabit per second transceiver generation, with a path toward what comes after. For context, 1.6T transceivers are the current frontier — you're doing 8 lanes at 200 gigabaud or 16 lanes at 100 gigabaud, depending on your approach. The power budget for a 1.6T pluggable today is uncomfortable. Bringing 2nm technology to the control logic is one of the cleaner paths to getting that power down to something you can actually deploy at rack scale. Skyler: The competitive dynamic here is fierce. Coherent, II-VI — now Coherent Corp — Broadcom, Intel, and a set of well-funded startups are all working on next-generation transceiver technology for A I fabric. Marvell bringing a 2nm platform into this fight is a statement about their seriousness in owning the optical silicon layer, not just the switching and SerDes layers where they've historically been strong. Skyler: And there's a vertical integration angle here too. Marvell has been building toward a position where they can offer a customer — say, a hyperscaler building a custom A I system — a coherent solution that covers the switch ASIC, the SerDes, and the optical engine. That's a powerful position if you can execute on it, because it simplifies the co-design problem enormously. Skyler: Watch this space closely. The 2nm optical demonstration is a technical milestone, but the real question is when it turns into shipping product and what the yield and cost profile looks like at volume. Demonstrations are necessary but not sufficient. Skyler: Last story, and this one is more nuts-and-bolts but arguably the most practically important for anyone actually building systems today. Semiconductor Engineering ran a deep-dive on system-level design for 1.6 terabits per second interoperability in A I datacenters. This is the kind of piece I love because it gets into the actual engineering tradeoffs rather than staying at the announcement layer. Skyler: So 1.6T interoperability is genuinely hard, and let me explain why "interoperability" is the specific word that matters here. It's easy to build a 1.6T link if you control both ends of it. You pick your SerDes, you tune your channel, you characterize your loss budget, and you validate the whole thing as a system. That's what every vertically integrated vendor does, and it works fine as long as both ends are from the same vendor. Skyler: Interoperability means your 1.6T switch port needs to work with a transceiver from a different vendor than the switch silicon, which needs to work with cable or fiber from yet another vendor, which needs to connect to a host adapter from a different vendor entirely. Each of those interfaces needs to conform to a common specification tightly enough that the end-to-end link actually functions at spec. At 1.6T, that's a hard problem. Skyler: The Semiconductor Engineering piece walks through the key system-level challenges. First is the channel itself — at 200 gigabaud, the electrical channel between your ASIC and the optical module is already lossy enough that you need very careful PCB design and often a retimer. The piece covers how that channel budget gets allocated across the board trace, the connector, and the module interface, and how different design choices affect the interop margin. Skyler: Second is forward error correction. At these lane rates, FEC is not optional — you're going to have raw bit errors and FEC is what cleans them up. But different FEC implementations have different latency profiles, and for A I collective operations where you're doing tight synchronization across thousands of accelerators, FEC latency is not a free variable. The piece discusses the tradeoffs between FEC strength and latency that system designers need to navigate. Skyler: Third is the signaling standard itself. The 200G per lane signaling that underpins 1.6T is defined across a few different specifications — IEEE 802.3 for the physical layer, OIF for the electrical interface between the module and the host, and then the MSA community for the module form factors. Getting all of those to align in a way that actually enables multi-vendor interop is a standards coordination challenge as much as an engineering challenge. Skyler: The Ultra Ethernet Consortium — U E C — is relevant context here. U E C is working on the transport and congestion control layer for A I scale-out networks, but the physical layer work has to happen in these other standards bodies. U E C assumes a functioning 1.6T physical layer underneath it. If that physical layer doesn't have clean interop, U E C's higher-layer work doesn't matter in practice. Skyler: The practical implication for system architects is that 1.6T interoperability is achievable but requires discipline. You need to choose your components carefully, you need to characterize your channels early, and you need to be in the room with your vendors doing multi-vendor interop testing well before your deployment timeline. The margin for "we'll figure it out at integration" is very thin at these speeds. Skyler: And for investors watching this space: the companies that crack multi-vendor 1.6T interoperability with clean, reliable, high-volume supply are going to be in a very strong position. Because hyperscalers don't want single-vendor lock on their transceiver supply chain. They want a competitive ecosystem. The technical bar for participating in that ecosystem is just genuinely high. Skyler: Alright, that's a wrap on today's Line Rate. Quick thread connecting everything we covered: optics are the critical path for next-generation A I fabric, the transition from pluggables to co-packaged is accelerating, and the system-level interoperability work at 1.6T is where a lot of the real engineering is happening right now. It's a genuinely exciting moment to be working in this space. Skyler: Line Rate is brought to you by Ada — helping organizations integrate A I into their real workflows — and Zen Semiconductor, an umbrella company with a portfolio of companies across the silicon industry. If you got value out of today's episode, please subscribe and share it with someone who's deep in the datacenter stack. Show notes with links to everything we discussed are at lineratepod.com. See you next time.